Inside the CAT25256 is an EEPROM serial 256-Kb SPI device organized as 32Kx8 bits. This has a 64-byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through the Chip Select (CS) input. In addition, a bus is required

The signals are the clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input can be used to suspend any serial communication with the CAT25256 device. The device features software and hardware write protection, including partial as well as full array protection. On-chip ECC (Error Correcting Code) makes the device suitable for high reliability applications.

feature

Compatible with 20 MHz (5 V) SPI

1.8 V to 5.5 V supply voltage range

SPI mode (0,0) and (1,1)

64 byte page write buffer

Additional identification pages with permanent write protection

Self-timed write cycle

Hardware and software protection

Block Write Protection - Protects 1/4, 1/2 or the entire EEPROM array

Low power CMOS technology

1,000,000 program/erase cycles

100 years data retention

Industrial and Extended Temperature Range

8-lead SOIC, TSSOP and 8-pad UDFN packages

The device is lead-free, halogen-free/BFR, RoHS

Functional Symbol Diagram

PIN configuration diagram

Pin Description

SI: Serial data input pin accepts opcode, address and data. In SPI modes (0,0) and (1,1), incoming data is latched on the rising edge of the SCK clock input.

SO: The serial data output pin is used to transmit data to the device. In SPI modes (0,0) and (1,1), data is shifted out on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock provided by the host for synchronous communication between the host and the CAT25256.

CS: Chip select input pin is used to enable/disable CAT25256. When CS is high, the SO output is tri-stated (high)

impedance) and the device is in standby mode (unless an internal write operation is in progress). Each communication session between the host and the CAT25256 must begin with a transition from high to low and end transition from low to high for the CS input.

WP: Write Protect input pin will allow all write operations to the device while high. Writing to the status register is disabled when the WP pin is low and the WPEN bit in the status register (see Status Register Description, later in this data sheet) is set to '1'.

HOLD: The HOLD input pin is used to suspend transmission between the host and the CAT25256 without retransmitting the entire sequence at a later time. To suspend, HOLD must be taken low and to resume it must be brought back high, with the SCK input low during both conversions. When the hold is not used, it is recommended to tie the HOLD input to VCC, either directly or through a resistor.

Synchronous data timing diagram

The CAT25256 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8-bit instruction register. Instructing to read the data stored in the CAT25256 is done by simply providing the READ command and the address. In addition to WRITE, writing CAT25256 commands, addresses and data also requires the device to be enabled for writing to first set certain bits in the state register, which will be explained later. After a high-to-low transition on the CS input pin,

The CAT25256 will accept any one of the six instructions for the communication protocol as shown in the sequence shown above.

CAT25256, the new product Rev E has an additional identification page (64 bytes) that can be accessed for read and write operations when the IPL bit is set to "1" from the status register. The user can also choose to permanently write-protect the identity page.

Once the WEL bit is set, the user can perform a sequence of write operations, by sending the WRITE command, a 16-bit address and data as shown in Figure 5. Only 15 significant address bits are used for the CAT25256. The 16th address bit is not, note the table below. Internal programming will begin after CS transitions low to high. Loop during internal write, all commands, except RDSR (Read Status Register) will be ignored. The RDY bit will indicate whether an internal write cycle is in progress (RDY high) or the device is ready to accept a command (RDY low). Sending the first data byte to the host CAT25256 can continue to send data, up to 64 bytes, following the timing shown in Figure 6. After each data byte, the low-order address bits are automatically incremented, while the high-order address bits (page address) are reserved

constant. If the page ends over in the process, then the load will "flip" to the first byte of the page, thus potentially overwriting previously loaded data. After completing the write cycle, the CAT25256 automatically returns to the write disabled state. While an internal write cycle is in progress, the RDSR command will output only the RDY (ready) bit status (ie, data out = FFh). write recognition page

An additional 64-byte identification page (IP) can be written with user data using the same Write command. The sequence used for page writes to the main memory array must set the IPL bit in the status register (IPL = 1) before attempting to write with the WRSR instruction Enter the IP.

The address bits [ A15 :A6] are Don't Care and the bits [A5:A0] define the byte address within the byte address identification page. In addition, the byte address must point to a location outside the protected area defined by BP1, the BP0 bit in the status register. When the full memory array is write-protected (BP1, BP0 = 1,1), writes are not accepted and commands to IP are not executed. Also, writes to IP are not accepted if the LIP bit is from the Status register set to 1 (page locked in read-only mode).