Negative 5-V 200 mA output (VCC≥4.5 4-V to 6.2-V input operating range 78% typical efficiency

The 160 kHz fixed frequency current mode pulse width modulation controller en input inhibits operation and reduces supply current to 1 µA.

Soft-Start 8-Pin SOIC and DIP Packages -40°C to 85°C Free Air Temperature Range Pin Compatible with MAX73

describe

The TPS6735 is a fixed negative 5V output inverting DC/DC converter capable of outputting 200mA from the input.

as low as 4.5 volts. The only external components required are an inductor, an output filter capacitor, and an input filter.

capacitors, reference filter capacitors, and Schottky rectifiers. An enable input is provided to shut down the inverter when the 8722 ; 5-V output is not required. Typical supply current is 1.9 mA at no load and decreases further.

1-µA when the enable input is low.

The TPS6735 is a 160 kHz current-mode pulse-width modulation (PWM) controller with P-channel MOSFET power switches. The gate driver uses a −5-V output to reduce the die area required to implement a 0.4-ohm MOSFET.

Soft start is done by adding a small capacitor to SS. The 1.22V reference voltage can be used for external loads up to 125µA.

The TPS6735 is attractive for computer peripherals and battery-powered board-level DC/DC conversion.

Devices requiring high efficiency and low supply current.

The TPS6735 is available in 8-pin DIP and SOIC packages and operates over the free air temperature range.

-40°C to 85°C.

Functional block diagram

Chip information

These chips, when properly assembled, show similar characteristics to the TPS6735. Thermocompression or ultrasonic welding can be used on doped aluminum pads. Chips can be mounted on conductive epoxy or gold silicon preforms

Detailed Description

The following description refers to functional block diagrams.

current sense amplifier

A fixed gain of 3 current sense amplifier amplifies the slope compensated current sense.

voltage (the sum of the current sense resistor and the voltage on the oscillator ramp) and enter it

PWM comparator.

drive latch

A latch consists of a set/reset flip-flop and associated logic that controls the state of the power switch by:

Turn the drive on and off. The high output of the latch turns on the switch; the low output turns off the switch. normal

The operation flip-flop is set high during the clock pulse, but the strobe keeps the latched output low until the clock pulse

ended. When the PWM comparator output goes high, the latch is reset.

enable (en)

A logic low on EN puts the TPS6735 in shutdown mode. During shutdown, the output power switch, voltage

The reference and other functions are turned off and the supply current is reduced to a maximum of 1-µA. soft start

The capacitor is discharged through a 1.2 megohm resistor and the output voltage drops to zero volts.

Error amplifier

The error amplifier is a high gain differential amplifier used to regulate the output voltage of the converter. By comparing the output samples, this amplifier generates an error signal, which is fed into the PWM comparator.

The difference between the reference voltage and the amplified voltage. The output samples come from a resistive divider.

Connect between FB and reference FB. FB is externally connected to the converter output, and the voltage divider output is connected to the error amplifier input. An 82 pF capacitor is required between COMP and GND to stabilize the control loop when the load is greater than 100 mA.

Oscillators and Ramp Generators

The oscillator circuit provides a 160 kHz clock to set the operating frequency of the converter, as well as a timing ramp slope compensation. The clock waveform is a pulse lasting hundreds of nanoseconds and is used to limit the maximum power switching duty cycle to 95%. The timing ramp is summed with the current sense signal at the input of the current sense amplifier.

An overcurrent comparator monitors the current in the power switch. The comparator trips and starts a soft-start cycle if the power switch current exceeds 2 A peak.

switch

The power switch is a 0.4 ohm P-channel MOSFET with current sensing. The drain is connected to the outdoor current sense is connected to a resistor. The voltage across the resistor is proportional to the current in the power supply.

The switch is connected to an overcurrent comparator and a current sense amplifier. In normal operation, the power switch is turned on at the beginning of each clock cycle and turned off when the PWM comparator resets the driver.

latch.

The PWM comparator resets the drive latch and turns off the power switch during slope compensation.

The current sense signal of the current sense amplifier exceeds the error signal.

refer to

The reference voltage is output at the reference voltage to provide a maximum of 125-µA power to external loads. A 10-µF capacitor is recommended between REF and GND to minimize noise pickup.

stainless steel clip

The SS clamp circuit limits the signal level of the error amplifier output during startup. The voltage on SS is amplified and used to override the error amplifier output until it is above that, at which point the error amplifier takes over. This prevents the signal input to the PWM comparator from exceeding its common-mode range.

(ie, the error amplifier output is too high to be reached by the current ramp) by limiting the amplifier output error during startup.

Soft-start causes the output voltage to increase to the regulation point at a controlled rate. The voltage on the charging soft-start capacitor gradually increases the clamp of the error amplifier output voltage, limiting the inrush current to energize by increasing the current limit threshold on a cycle-by-cycle basis. A soft-start cycle is when the enable (EN) signal is toggled high or an overcurrent fault condition triggers the discharge of the soft-start capacitor.

Under Voltage Lockout (uvlo)

The supply voltage is input to the UVLO through a voltage divider and compared to a reference voltage. This undervoltage lockout logic prevents when the supply voltage is below the undervoltage lockout voltage threshold, once the supply voltage on VCC is above the threshold, SS cycling has been initiated.

Dissipation Ratings Table

PackagingTa≤25°C

rated power

Derating factor

Ta=25°C or more

Ta=70°C

rated power

Ta=85°C

rated power

D 725 MW 5.8 MW/°C 464 MW 377 MW P 1175 MW 9.4 MW/°C 752 MW 611 MW Absolute Maximum Ratings Over Operating Free Air Temperature Range (unless otherwise noted)† Stresses in excess of the Absolute Maximum Ratings may cause permanent damage to the device. These are pressure ratings only, and functional operation of the device is not implied under these or any other conditions shown in "Recommended Operating Conditions". Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Note 1: All voltage values are related to network terminal G.

Operates in a voltage-inverting circuit as shown in the TPS6735, which produces a −5-V output.

This circuit is ideal for input and output applications that require negative polarity voltages.

Ground and energy management systems. The TPS6735 can be put into shutdown mode (1-µA quiescent current).

soft start

The soft-start capacitor provides orderly converter startup by slowly increasing the switch current limit.

during power up. Soft-start timing is controlled by the SS capacitor. The switch current limit is proportional to the applied voltage to SS, internally pulled to the reference by a 1.2 MΩ resistor. SS can be pulled out below the limit reference.

switch current. The uvlo state or overcurrent state initiates the ss cycle by releasing the ss.

The capacitor is connected to ground through an internal transistor. A capacitor of at least 10 nF must be connected to SS to properly limit the current.

Sensor selection

The saturation current of the standard 10µh inductor required by the TPS6735 must be greater than the peak value.

Switch the current at the desired maximum load. Ensure operation over the full voltage range and current range through the 10-µH inductor. To determine the required inductor state level, see Typical Operation.

Inductor peak current and load current characteristic diagram

application information

output filter capacitor

To minimize output ripple, a low equivalent series resistance (ESR) output filter capacitor is required.

Voltage. An ESR of 100 MΩ limits output ripple to 90 mV or less with output loads up to 200 mA.

Rectifier

A Schottky diode or high speed silicon rectifier should have a maximum continuous current rating of 1 A for full load operation (200 mA).

Output Ripple Filtering

A low-pass filter can be added at the converter output to reduce output voltage ripple. The cutoff frequency of this LC filter is 7.2 kHz. The inductor filter must have low resistance to avoid large outputs.

voltage drop. When using the LC output filter, the output voltage ripple is reduced to 5 mV. The low pass filter must be connected before the FB is connected to the output node.

printed circuit board layout

It is recommended to use a ground plane in the printed circuit board (PCB) layout to ensure quiet operation. WARNING The length of the switch loop should be minimized. Bypass capacitors should be placed as close as possible to the TPS6735 to prevent instability and noise pickup. VCC and GND should be bypassed directly with 1-µF ceramic capacitors and large bypass capacitors (for example, 47µF) to maximize noise immunity. This TPS6735 should not be used with IC sockets, wire wrap templates or other structures.

susceptible to noise