feature
CCD Signal Processing – Correlated Double Sampling (CDS)
– Programmable Black Clamp Programmable Gain Amplifier (PGA)
––6-db to 42 db gain range
10-Bit Digital Data Output – Up to 36 MHz Conversion Rate – No Missing Codes
76dB SNR Portable Operation – Low Voltage: 2.7 V to 3.6 V
– Low power: 130 mW at 3.0 V (typ.)
– Standby Mode: 6 MW Description
The VSP2232 is a complete mixed-signal processing IC.
An array of analog-to-digital conversions used to provide signal conditioning and CCD output. The main CCD channel provides correlated double sampling (CD) to extract video information from pixels, A – 6-db to 42 db gain, with digital control for different lighting conditions and black level clamping for accurate black level reference.
The clamping of the input signal and the offset correction of the input also perform CDS. Stable gain control is linear.
Unit: dB. Also, blackness recovers quickly after a gain change.
VSP262Y (12-bit 20 MHz) single-chip product.
The VSP232Y is available in a 48-pin LQFP package.
Powered by a single 3-V/3.3-V supply.

VSP2232 block diagram

Detailed description introduction
The VSP2232 is a complete mixed-signal integrated circuit containing all key functions related to processing.
CCD imager output signals in video cameras, digital still cameras, security cameras or similar devices.
application. The first page of this data sheet shows a simplified block diagram.

The VSP2232 includes correlated double sampling (CDS), programmable gain amplifier (PGA), analog-to-digital converter (ADC), input clamp, optical black (OB) level clamp loop, serial interface, timing control and reference generation device. We recommend having an off-chip emitter follower buffer between the CCD output and the VSP2232.

CCDIN input. PGA gain control, clock polarity setting, and operating mode selection are available.
via the serial interface. When the reset pin goes low, all parameters are reset to default values.
Asynchronous from the clock.

Correlated Double Sampler (CDS)
The output signal of the CCD imager is sampled twice during one pixel period, once at the reference interval and another at the data interval.
Subtract these two samples, extract the video information of the pixel, and remove the same or related to these two intervals.
Therefore, CD is very important to reduce reset noise and low frequency noise
CD is driven through an off-chip coupling capacitor (CIN). AC coupling is strongly recommended because the DC level of the CCD output signal is often too high (a few volts) for the CD to work properly. 0.1-micro FCIN capacitor is recommended, but depends on application environment

Correlated Double Sampler (CDS) (continued)
In addition, it is recommended to use an off-chip emitter follower buffer capable of driving more than 10 pF, as sampling capacitance and a small amount of stray capacitance can be seen at the input. The analog input signal CCDIN pin has a range of 1 Vp–p, the appropriate common mode voltage for CD is approximately 0.5 V to 1.5 V
The reference level is sampled during SHP activation and the voltage level is held across the sampling capacitor.
(1) At the trailing edge of the SHP. The data level is sampled during SHD activation, and the voltage level is fixed on the sampling capacitor C(2) on the trailing edge of the SHD. The switched capacitor amplifier then performs these two levels of subtraction.
The activation polarity (active high or active low) of the SHP/SHD can be selected via the serial interface, see Serial Interface for details. The default value for SHP/SHD is active low. However, after power up, this value is unknown. Therefore, it must be set to the appropriate value using the serial interface, or reset to the default value of the reset pin. The descriptions and timing diagrams in this datasheet are based on low polarity activation (default).
The input clamp and dummy pixel clamp buffered CCD output capacitors are coupled to the VSP2232. The purpose of the input clamp is to restore the DC component of the input signal, which is lost with AC coupling, and establish the desired DC bias point.
For CDs. The input level is fixed at the internal reference voltage reference value (1.25 V) during the virtual pixel interval. More specifically, when two CLPDM
After SHP activation, the pseudo-clamp function is activated. If dummy pixels and/or CLPDM pulses are not available in your system, CLPOB pulses can be used in place of CLPDM as long as they are clamped.
Occurs during black pixels. In this case, the CPLDM pins (active in synchronization with CLPOB) and SHP become active during the optical black pixel interval, and then the virtual clamping function becomes active.
The active polarity of CLPDM and SHP (active high or active low) can be selected via the serial interface.
See Serial Interface for details. The default value for CLPDM and SHP is active low. However, after the power is on, this value is unknown. Therefore, it must be set to the appropriate value using the serial interface, or reset to the default value by resetting the pins. The descriptions and timing diagrams in this datasheet are based on active low polarity (default).
High-performance analog-to-digital converters The analog-to-digital converters (ADCs) are fully differential and pipelined. This ADC is well suited for low voltage operation, low power requirements and high speed applications. It guarantees 10-bit resolution of output data with no missing codes. The VSP2232 includes a reference voltage generator for the ADC. refp (positive reference, pin 38), refn (negative reference, pin 39) and cm (common mode voltage (pin 37) should be bypassed to ground with 0.1-microF ceramic capacitors. Do not use this voltage anywhere else in the system , as it will affect the stability of these reference levels and then cause the ADC to degrade. These are analog output pins, so don't apply voltage externally.

Programmable Gain Amplifier (PGA)
Characteristics of PGA gain. The PGA provides a gain range of -6 dB to 42 dB, which is linear in decibels. Gain is controlled by a digital code with 10-bit resolution and is available via the serial interface, see the Serial Interface section for details. The default value of the gain control code is 128 (pga gain = 0 dB). However, after power up, this value is unknown. Therefore, it must be set to the appropriate value using the serial interface, or reset to the default value via the reset pin Optical Black (OB) level clamp ring. In order to correctly extract the video information, the CCD signal must be referenced to a Mature optical black.
(OB) level. The VSP22232 features an auto-calibration loop to establish OB levels using optical black pixels.

output from the CCD imager. The input signal level of the OB pixel is identified as the actual OB level and when CLPOB is active, the loop should be closed during this period. During the valid pixel interval, the level of the reference CCD output signal is clamped to the OB level by the OB level clamp loop. To determine the loop time constant, an off-chip capacitor is required and should be connected to COB (pin 28). time constant t
c is the value of the capacitor connected to COB, i(min) is the clamp loop that controls the DAC at the OB level, 0.15μA is equivalent to 1 LSB of the DAC output current. When C is 0.1 μF, the time constant t is 40.7 μs. Also, the slew rate (sr) is given in Equation 2.
C is the value of the capacitor connected to COB. i(max) is the control DAC in the OB level clamp loop, 153 microamps is equivalent to 1023 LSB of DAC output current.
Typically, OB-class gripping at high speeds results in gripping noise (or white streak noise). However, the noise will be reduced by increasing the capacitor size. On the other hand, larger capacitors take longer to recover from standby mode, or immediately after power is turned on. Therefore, we recommend a 0.1-µF to 0.22-µF Capcitor. However, it depends on the application environment and a trial cut method is recommended.

Pre-Blanking and Data Delay

During the blanking interval, some common devices have large transient output signals. These signals may exceed the VSP23232's 1-VP input signal range and will overdrive the VSP2222 into saturation. Recovery time from saturation can be long. To avoid this, the VSP2232 has an input blanking (or pre-blanking) function. When PBLK goes low, the CCDIN input is disconnected from the internal CDS stage, preventing large transients from passing through. The digital outputs of the vsp2232 will go to all zeros after the 11th rising edge of adcck from pblk set low to accommodate the clock delay of the vsp2232. In this mode, digital output data is output from the rising edge of ADCCK with a delay of 11 clock cycles (data delay of 11). In normal operating mode, it is different from pre-blanking mode. The digital output data is output on the rising edge of ADCCK with a delay of 9 clock cycles (data delay of 9).

To keep OB clamping stable and accurate, CLPOB should not be activated during PBLK activation. Since the CCDIN input is disconnected from the internal circuit, the auto-calibration loop should be closed even when CLPOB is active. Then, the OB clamp level is different from the actual OB level established by the CCD imager output. Lost OB clamps can affect image quality.

If the input voltage is 0.3 V above the power rail or 0.3 V below the ground rail, the protection diodes turn on to prevent the input voltage from rising further. Such a high swing signal may cause equipment damage to the VSP2232 and should be avoided.

Detailed Description (Continued) Standby Mode In order to save power, when the VSP2222 is not in use, the VSP2222 can be set to standby mode (or power-down mode) through the serial interface. See Serial Interface for details. In this mode, all function blocks are disabled and the digital outputs will become all zeros. The current consumption will drop to 2 mA. Since all bypass capacitors will discharge in this mode, it takes a considerable amount of time (typically 200 ms to 300 ms) to recover from standby mode.

voltage reference

All reference voltages and bias currents required by the VSP22232 are generated by its internal bandgap circuitry. The CDS and ADC use three reference voltages: refp (positive reference voltage, pin 38), refn (negative reference voltage, pin 39), and cm (common mode voltage, pin 37). All refp, refn, and cm should be heavily decoupled with appropriate capacitors (eg: 0.1-microF ceramic capacitors). Do not use these voltages anywhere else in the system as it will affect the stability of these reference levels and cause degradation in ADC performance. These are analog output pins, so don't apply voltage externally.

BYPP2 (Pin 29), BYP (Pin 31) and BYPM (Pin 32) are also reference voltages used in analog circuits. BYP should use a 0.1-µF ceramic capacitor to ground. The capacitance values of bypp2 and bypm affect the step response. We believe that 200 pf to 600 pf is a reasonable value for many applications. However, it depends on the application environment and a "cut and try" method is recommended for careful adjustment. All bypp2, byp and bypm should be heavily decoupled with proper capacitors. Do not use these voltages anywhere else in the system as it will affect the stability of these reference levels and cause performance degradation. These are analog output pins, so don't apply voltage externally.

Additional output delay control

VSP22232 can control the delay time of output data through register setting through serial interface. In some cases, the transformation of output data can affect simulation performance. Usually, this is avoided by adjusting the timing of ADCCK. In cases where ADCCK timing cannot be adjusted, this output delay control can effectively reduce the effects of transient noise. See Serial Interface for details.

The serial interface has a 2-byte shift register and various parallel registers to control all digital programmable functions of the VSP2232. Writing to these registers is controlled by four signals (sload, sclk, sdata, and reset). To enable the shift register, sload must be pulled low. sdata is the serial data input and sclk is the shift clock. The data of SData is brought into the shift register on the rising edge of SCLK. The data length should be 2 bytes. After a 2-byte shift operation, the data in the shift register is transferred to the parallel latch on the rising edge of sload. In addition to the parallel latches, there are several registers dedicated to device-specific functions that are synchronized to the ADCCK clock. Writing data from the parallel latches to these registers takes 5 to 6 clock cycles. Therefore, in order to complete the data update, it must wait five to six clock cycles after the parallel latch on the rising edge of SLOAD.

The VSP2232 has two options for driving the on-chip A/D converter. Accessing the configuration registers via the serial interface allows selection of internal drive mode and external drive mode. The internal drive mode, that is, the drive clock of the A/D converter, is automatically generated by the on-chip timing control circuit according to the SHP and SHD signals. The external drive mode is the main clock (ADCCK), which directly drives the on-chip A/D converter. The digital data output is synchronized to the master clock (ADCCK) regardless of drive mode.

The CDS and ADC are operated by the SHP/SHD, and their derived clocks are generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. The timing relationship between the CCD signal, SHP/SHD, ADCCK, and output data is shown in the VSP2222 CDS timing specification. CLPOB is used to activate the black level clamp loop during OB pixel intervals and CLPDM is used to activate the input clamp during dummy pixel intervals. If CLPDM pulses are not present in the system, CLPOB pulses can be used in place of CLPDM as long as clamping occurs during black pixels, see Input Clips and Virtual Pixel Clips for details. The clock polarity of SHP/SHD, CLPOB, CLPDM can be independently set through the serial interface, see the serial interface section for details. The descriptions and timing diagrams in this datasheet are based on active low polarity (default). To maintain stable and accurate OB clamping, it is recommended not to activate CLPOB during PBLK activation. For more information, see Preblanking and Data Delay. In standby mode, ADCCK, SHP, SHD, CLPOB and CLPDM are internally masked and pulled high.

Power, Ground, and Equipment Decoupling Recommendations

The VSP22232 integrates a very high precision and high speed analog-to-digital converter and analog circuitry that is susceptible to any extraneous noise from the track or elsewhere. Therefore, although the VSP2232 has both analog and digital power pins, it should be considered an analog component, and all power pins except the DRV should be powered only by the system's analog power supply. This will ensure the most consistent results, as digital power lines tend to carry high levels of broadband noise that would otherwise couple into the device and degrade achievable performance. DD

Proper grounding, short lead lengths, and the use of ground planes are also important for high-frequency designs. For best performance, multilayer PC boards are recommended as they offer distinct advantages such as reduced ground impedance, separation of signal layers by ground planes, etc. It is strongly recommended to connect the analog and digital ground pins of the VSP2232 on the IC and only to the analog ground of the system. . The driver stage for the digital output (B(11:0)) is powered through a dedicated power supply pin (DRV) and should be completely separated from the other supply pins, or at least separated by ferrite beads. It is also recommended to minimize capacitive loading on the output data lines (typically less than 15 pF). Larger capacitive loads require higher charging currents due to surges that feed back to the analog portion of the VSP2232 and affect performance.

If possible, external buffers or latches should be used to provide the added benefit of isolating the VSP2232 from any digital noise activity on the data lines. Additionally, the resistors in series with each data line help minimize inrush current. A value in the range of 100Ω to 200Ω will limit the instantaneous current of the output stage and must recharge the parasitic capacitance when the output level changes from low to high or from high to low. Due to the high speed of operation, the converter also generates high frequency current transients and noise, which can be fed back into the power and reference lines. This requires adequate bypassing of the supply and reference pins. In most cases, a 0.1-µF ceramic chip capacitor is sufficient to decouple the reference pin. The power pins should be separated from the ground plane using a parallel combination of tantalum (1 microF to 22 microF) and ceramic (0.1 microF) capacitors. The effectiveness of decoupling depends largely on the proximity of the individual contact pins. DRV should be separated from adjacent positions of DRVgnd. Special attention must be paid to bypassing COB, BYPP2, and BYPM, as these capacitance values determine the important analog performance of the device.

timing specification

Mechanical data
PT (S-PQFP-G48) Plastic Quad Flat Package

Note: a. All linear dimensions are in millimeters.
B. This picture is subject to change without notice.
c. Belong to JEDEC MS-026
d. This can also be a thermally reinforced plastic package with leads connected to the die pads.