0-V input accuracy Zero reading for zero detection, true polarity is 0 1-pa typical input current True differential input Multiplexed binary coded decimal (BCD) output Low rollover error: ±1 count Maximum control signal allowed with UART or Micro Processor interface with TTL-compatible automatic ranging capability for over-range and under-range signals.

illustrate
The ICL7135C and TLC7135C converters are fabricated using Texas Instruments' high-efficiency CMOS technology. This 4 1/2-bit, dual-slope integrated, analog-to-digital converter (ADC) design provides an interface to a microprocessor and a visual display. Digital driver outputs d1 to d4, and multiple binary coded decimal outputs b1, b2, b4, and b8 provide an interface for LED or LCD decoder/drivers and microprocessors.
The ICL7135C and TLC7135C offer 50 ppm (1 in 20000) resolution with a maximum linearity error of one count. The zero point error is less than 10μV, and the zero point drift is less than 0.5μV/°C. Source impedance error is minimized by low input current (less than 10 Pa). Rolling error is limited to ±1 count.
Busy, strobe, run/hold, overrange, and underrange control signals support microprocessor-based measurement systems. Control signals can also support remote data acquisition systems that transmit data via a Universal Asynchronous Receiver Transmitter (UART). The ICL7135C and TLC7135C are characterized for operation over a temperature range of 0°C to 70°C.

Functional block diagram

Principle of Operation
The measurement cycle of the ICL7135C and TLC7135C includes the following four stages.
1. Auto zero phase. Internal input + and input are disconnected from the terminal and connected internally to ANLG common. The reference capacitor is charged to the reference voltage. The system uses a closed-loop structure to charge the auto-zero capacitor to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Auto-zero accuracy is limited only by system noise and total offset (as input) is less than 10µV.
2. Signal integration phase. The auto-zero loop is open and the internal input + and input are connected to the external terminals. The differential voltage between these inputs is integrated for a fixed time. Can be connected to Anlg Common when the input signal has no return relative to the converter power supply to establish the correct common mode voltage. After completing this stage, record the polarity of the input signal.
three. de-integration stage. References are used to perform deintegration tasks. Internal In 8722 ; internally connected to ANLG common, while In+ is connected through a previously charged reference capacitor. The recording polarity of the input signal ensures that the capacitors are connected with the correct polarity to return the integrator output polarity to zero. The time required for the output to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital readout, determined by the equation 10000 × (VID/VREF). The maximum or full-scale transition occurs when VID is twice VREF. 4. Zero integrator phase. The internal input is connected to ANLG common. The system is configured in a closed loop so that the integrator output returns to zero. Typically, this stage requires 100 to 200 clock pulses. However, after the overrange transition, 6200 pulses are required.

Analog Circuit Description Input Signal Range The common-mode range of an input amplifier extends from 1 V above the negative supply to 1 V below the positive supply. In this range, the common mode rejection ratio (CMRR) is typically 86 dB. Both differential and common-mode voltages cause the integrator output to swing. Therefore, care must be taken to ensure that the integrator output does not saturate.
Analog Common The analog common (ANLG common) is connected to the internal input during the autozero, deintegrate, and zero integrator stages. During the signal integration phase, the amplifier rejects the resulting common-mode voltage when the input is connected to a voltage different from the analog common. In most applications, however, In− is set to a known fixed voltage (eg, common power). In this application, the analog common should be tied to the same point to remove the common-mode voltage from the converter. Removing the common-mode voltage in this way slightly improves conversion accuracy.
The reference voltage is positive with respect to analog common. The accuracy of the conversion result depends on the quality of the reference. Therefore, to obtain high-precision conversions, a high-quality reference should be used.
Digital Circuit Description Run/Hold Input When Run/Hold is high or on, the unit continuously performs a measurement cycle every 40002 clock pulses. When this input is turned low, the integrated circuit continues to perform a continuous measurement cycle and then holds the conversion reading for as long as the terminal remains low. After completing a measurement cycle, a short positive pulse (greater than 300 ns) starts a new measurement cycle while the terminal is held low. When this positive pulse occurs before the measurement period is complete, it will not be recognized. The first strobe light pulse occurs 101 counts after the end of the measurement period, indicating the end of the measurement period. Therefore, after the first strobe pulse, a positive pulse can be used to trigger the start of a new measurement.
Strobe Input A negative-going pulse on this input transfers the BCD conversion data to an external latch, UART, or microprocessor. At the end of the measurement period, the strobe light goes high and remains high for 201 counts. The most significant bit (msd) bcd bit is placed on the bcd terminal. After the first 101 counts, the strobe terminal goes low at 1/2 the clock pulse width while outputs d1−d5 go high. Placing the strobe at the midpoint of the high pulse on D5 can latch information into an external device on a low or edge. This placement of the strobe light pulse also ensures that the BCD bit of the second MSD has not yet competed with the BCD line and ensures that the correct bit is latched. Repeat the above process for the second MSD and D4 output. Again, the process repeats through the least significant bit (LSD). Subsequently, d5 to d1 are input, and the BCD line continues to scan without the strobe. Subsequent consecutive scans keep the conversion results displayed. When an out-of-range condition occurs, this subsequent scan does not occur.

Busy Output At the beginning of the signal integration phase, the busy output goes high. Busy remains high at the end of the first clock pulse after a zero crossing or at the end of the measurement period in the event of an overrange condition. Conversion results can be transferred serially using a busy terminal. Serial transfers can be sent and output by stabilizing busy and clock signals. The output of the transfer consists of 10001 clock pulses, which occurred during the signal integration phase, and the number of clock pulses that occurred during the deintegration phase. Subtract 10001 from the total number of clock pulses to get the conversion result.
Overrange Output When an overrange condition occurs, this terminal goes high after the busy signal goes low at the end of the measurement period. As previously mentioned, when an overrange condition occurs, the busy signal remains high until the end of the measurement period. At the end of the busy, the overrange output goes high and in the next measurement cycle it goes low at the beginning of the de-integration phase.
Underscale Output At the end of the busy signal, this terminal goes high when the conversion result is less than or equal to 9% of the full scale range (in 1800 counts). At the beginning of the signal integration phase of the next measurement cycle, the underrange output is reduced.
Polarity Output The polarity output of the positive input signal is high and updated at the beginning of each deintegration stage. Polarity outputs are valid for all inputs, including ±0 and overrange signals.
Digital driver (d1, d2, d4, and d5) outputs For 200 clock pulses, each digital driver output (d1 to d5) goes high in sequence. This sequential process is continuous unless an out-of-range condition occurs. When an overrange occurs, all digital driver outputs are masked from the end of the strobe sequence until the beginning of the deintegration phase (when continuous digital driver activation begins again). Blanking activity during an overrange condition can cause the display to flicker and indicate an overrange condition.
BCD outputs BCD bits (b1, b2, b4, and b8) for a given number are activated sequentially on these outputs. At the same time, the appropriate digit drive line is activated for the given digit.
The value of the integrating resistor (RINT) on the system side is determined by the full-scale input voltage and output current of the integrating amplifier. The integrating amplifier can deliver 20 microamps of current with negligible nonlinearity. The formula for determining this resistance value is:
International full-scale voltage integrating amplifier current iInt from 5 to 40 microamps yields good results. However, the rated and recommended current is 20 microamps.

Integrating capacitors should be selected with integrated resistors and capacitors to provide maximum voltage swing without causing the integrated amplifier output to saturate and get too close to the supply voltage. Saturation occurs when the amplifier output is within 0.3V of either supply. Designers should design a ±3.5-V to ±4-V integrating amplifier swing with ±5-V supplies and ANLG common ground. The rated capacitor value is 0.47 microF. The equation used to determine the integrating capacitor (CINT) value is:
C
International
10000 clock cycles I
Integral output voltage swing where iInt is nominally 20µA.
Capacitors with large tolerances and high dielectric absorption can cause conversion errors. Too small a capacitor can cause the integrating amplifier to saturate. High dielectric absorption results in different effective capacitance values during signal integration and de-integration stages. Polypropylene capacitors have very low dielectric absorption. Polystyrene and polycarbonate capacitors have higher dielectric absorption but also work well.
Auto-Zero Reference Capacitors Large capacitors help reduce noise in the system. Dielectric absorption is not important except during power-up or overload recovery. Typical value is 1 microF.
Reference Voltage For high-precision absolute measurements, a high-quality reference should be used.
Flip Resistors and Diodes
The rollover error of the ICL7135C and TLC7135C is small, but correctable. The way to correct it is to connect the cathode of any silicon diode to the int output and the anode to the resistor. The other end of the resistor is connected to ANLG common or ground. For recommended operating conditions, the resistance value is 100 kΩ. This value can be changed to correct any uncorrected scrolling errors. In many non-critical applications, resistors and diodes are not required.
Maximum Clock Frequency For most dual-slope A/D converters, the maximum conversion rate is limited by the frequency response of the comparator. In this circuit, the comparator follows the integrator ramp with a delay of 3 microseconds. Therefore, for a clock frequency of 160 kHz (6 microsecond period), half of the first reference integration clock period is lost in the delay. So the meter reading goes from 0 to 1 at 50µV input, 1 to 2 at 150µV input, 2 to 3 at 250µV input, and so on. This transition at the midpoint is desirable; however, when the clock frequency increases significantly above 160 kHz, even when the input is shorted. The transition points above assume a 2-V input range equal to 20,000 clock cycles.
When the input signal is always one polarity, the comparator delay need not be limited. A clock frequency of 1 MHz is possible because nonlinearity and noise do not increase significantly with frequency. For a fixed clock frequency, the extra counts due to the comparator delay is a constant that can be subtracted digitally.
For signals with two polarities, a low value resistor in series with the integrating capacitor can extend the clock frequency beyond 160 kHz without error. This resistor makes the integrator jump slightly toward the zero-crossing level at the beginning of the deintegration phase, compensating for the comparator delay. This series resistance should be 10Ω to 50Ω. This method allows clock frequencies up to 480 kHz.

Minimum Clock Frequency The minimum clock frequency limit is caused by auto-zero and capacitor leakage from the reference capacitor. Measurement periods of up to 10 microseconds are unaffected by leakage errors.
Reject 50 Hz or 60 Hz pickup To maximize rejection of 50 Hz or 60 Hz pickup, the clock frequency should be chosen so that integer multiples of the 50 Hz or 60 Hz period occur during the signal integration phase. To suppress these signals, some clock frequencies that can be used are:
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.
Zero-Crossing Trigger This flip-flop interrogates the zero-crossing state of the comparator. The interrogation is made after the previous clock cycle, and the positive half of the ongoing clock cycle has already occurred, so any comparator transients generated by the clock pulse will not affect the zero-crossing detection. This process delays the zero-crossing detection by one clock cycle. To eliminate inaccuracies caused by this delay, the counter is disabled for one clock cycle at the beginning of the deintegration phase. Therefore, when a zero crossing is detected one clock cycle later than the actual zero crossing, the correct count is displayed.
The peak-to-peak noise around noise 0 is about 15 μV (peak-to-peak value does not exceed 95% of the time). Near full scale, this value increases to about 30µV. Most of the noise originates from the auto-zero loop and is proportional to the ratio of the input signal to the reference signal.
Analog and Digital Grounds For high precision applications, ground loops must be avoided. Return currents from digital circuits must not be sent to analog ground.
Power Supplies The ICL7135C and TLC7135C are designed to work with ±5 V supplies. However, 5-V operation is possible when the input signal does not vary by more than ±1.5 V from the mid-supply.

Tape and Reel Information