The EL7562 is an integrated synchronous buck regulator whose output voltage is adjustable from 1.0V to 3.8V. It is capable of delivering 2A continuous current with up to 95% efficiency. The EL7562 operates in a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented on-chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, overcurrent protection and excellent step load response. The EL7562 is available in a molten lead 16 Ld QSOP package. With appropriate external components, the entire converter fits into a zone 2 that is smaller than 0.5. The few external components and small size make this EL7562 suitable for desktop and portable applications. The EL7562 is specified over the 0°C to +70°C temperature range.

block diagram

The EL7562 is a fixed frequency, current mode controlled DC-DC converter with integrated N-channel power MOSFETs and a high precision reference. The device integrates all the active circuitry needed to implement a cost-effective, user-programmable 2A synchronous step-down regulator suitable for DSP core power use. Working Principle The EL7562 is composed of 5 main modules: 1. PWM controller 2. NMOS power FET and driver circuit 3. Bandgap reference 4. Oscillator 5. Thermal shutdown

The EL7562 PWM controller regulates the output voltage by using current mode control pulse width modulation. The three main elements in the PWM control are the feedback loop and the reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter to control the average value of the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the average output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems, current-mode control uses a dual feedback loop to provide output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty cycle in response to changing line or load conditions. Since the output voltages are equal time-averaged the output power of the modulator finds a relatively large LC time constant for supplying applications usually resulting in low bandwidth and poor transient response. By directly monitoring changes in the controller's reaction time through a series of resistors that sense the inductor current, the reaction time is not entirely limited by the output LC filter and can react more quickly to changing voltage and load conditions. This feedforward feature also simplifies the overall loop response due to the addition of a zero to the AC loop compensation. By choosing an appropriate current-to-voltage feedback ratio, the overall loop response will approximate a unipolar system. The resulting system offers several advantages over conventional voltage control systems, including simple loop compensation, pulse-by-pulse current limiting, quick response to line changes and good load step response. The heart of the controller is a direct summation of the inputs that compares its total voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is used to prevent the system from occurring in current-mode unstable topologies operating at duty cycles greater than 50%, and is also used to define the open-loop gain of the overall system. Slope compensation is internally fixed and optimized for inductor ripple current of 500mA. Power supply tracking does not aid steady-state operation of any input to the comparator. The current feedback is switched by the high-side switching of the current flowing in the sense inductor within the patented sensing scheme when it is in progress. Whether the high-side NMOS switch is turned on at the beginning of each oscillator cycle. The comparator input gate is closed for a minimum period of approximately 150ns (LEB) after the high side switch is turned on to allow the system to settle. Leading edge blanking (LEB) prevents false detection of voltages at the comparator inputs due to switching noise. The secondary overcurrent comparator terminates the high-side switching time if the inductor current exceeds the maximum current limit (ILMAX). If I LMAX has not been reached, the output from the regulator gets the feedback voltage FB to the voltage VOUT then, relative to the internal feedback reference voltage. The resulting error voltage is summed with the current feedback and slope compensation ramps. The high-side switch remains on until all four comparator inputs sum to zero, at which point the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty cycle of the high-side switch is limited to 95%. To eliminate cross-conduction of the high-side and low-side switches a 15ns break-before-make delay is incorporated in the switch driver circuit. The output enable (EN) input allows the regulator output to be deactivated by an external logic control signal. However, due to the relatively low open loop gain in the system, the gain will occur as the output voltage and loop-error gain is changed. This is shown in this performance curve. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating.

pin

NMOS power FET and driver circuit

The EL7562 integrates a low on-resistance (60mΩ) NMOS field effect transistor to achieve high efficiency, at 2A in order to use an NMOS switch for the high-side driver, the gate voltage needs to be driven higher than the source voltage (LX). This is done by bootstrapping the V HI pin above the LX voltage with an external capacitor CVHI and internal switches and diodes. When the low-side switch is turned on, the voltage to LX is close to the GND potential, and the capacitor CVHI is charged through the internal switch VDRV, which is generally 5V. At the beginning of the next cycle the high side switch turns on and the LX pin begins to rise from GND to VIN potential. The positive plate VHI of capacitor C as the LX pin rises immediately, eventually reaching the value of VDRV+VIN which is typically 10V, for VDRV=VIN=5V. This voltage is then level shifted and used to drive the gate of the high-side FET, through the VHI pin. A CVHI value of 0.1 μF is recommended.