Features Description The TPS54325 device is an adaptive real-time d1 d-cap2 mode that enables fast transient cap2 mode synchronous buck converters. The corresponding TPS54325 device enables system designers to have low output ripple and allows the ceramic output to complete a power capacitor bus regulator kit for various end equipment, with a low cost, low component count, low standby current solution. Wide VCC input voltage range: 4.5 V to 18 V Wide VIN input voltage range: 2.0 V to 18 Vv The main control loop of the TPS54325 uses DCAP2 mode control to provide a very fast output voltage range: 0.76 V to 5.5 V Transient response, no external components. The high-efficiency integrated FET optimized for the TPS54325 also features a dedicated circuit that enables lower duty cycle applications – 120 M (high device fits low equivalent series side) and 70 M (low side) resistance (ESR) output capacitors such as High Efficiency, Sub-10µA POSCAP or SP-CAP in Shutdown, Ultra Low ESR Ceramic Capacitors. The device operates from a 4.5-V to 18-V initial bandgap reference precision high VCC input, and a 2.0-V to 18-V VIN input power adjustable soft-start supply voltage. The output voltage can be pre-biased soft-start from 0.76V to 5.5V. The unit also features an adjustable slow start time and a 700kHz switching frequency (FSW) power-good feature. The TPS54325 is available in a cycle-by-cycle overcurrent limited 14-pin HTSSOP package and is designed to output power well over the -40°C to 85°C range. 2 Application Device Information (1) Part Number Package Body Dimensions (NOM) Widely used in low voltage systems TPS54325 HTSSOP (14) 5.00 mm x 4.40 mm – Digital TV Power Supply.

Overview

The TPS54325 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-Cap2 mode control. The fast transient response of the D-Cap2 controller reduces the output capacitance required to meet specific performance levels. Proprietary internal circuitry allows the use of low ESR output capacitors, including ceramic and special polymer types.

Functional block diagram

Function description

Soft-Start and Pre-Biased Soft-Start The TPS54325 has adjustable soft-start. When the EN pin goes high, the 2.0A current starts charging the capacitor connected from the SS pin to GND. During startup, the output voltage remains smoothly controlled. The equation for slow start time is shown in Equation 1. The VFB voltage is 0.765 V, and the SS pin source current is 2 μA.

The TPS54325 contains a unique circuit to prevent current being drawn from the output during start-up with the output pre-biased. When the soft-start command voltage is above the pre-bias level (internal soft-start is greater than the feedback voltage (VFB)), the controller slowly activates synchronous rectification by starting the first low-side FET gate drive pulse with a narrow turn-on time . It then increments the time by cycles until it coincides with the time specified by (1-d), where d is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, ensures the start-up and smooth rise of the output voltage (VO), and enables the control loop to transition from pre-bias start-up to normal operation.

good power

The TPS54325 has good output power. After the soft-start is complete, the power-good function is enabled. If the output voltage is within -10% of the target value, an internal comparator detects a power good state and the power good signal goes high. The RPG resistor value connected between PG and VREG5 is required to be 20 kΩ to 150 kΩ. If the feedback voltage is below 15% of the target value, the power good signal goes low after an internal delay of 10µs.

Output discharge control

The TPS54325 releases the output when en is low or the controller is turned off by protection functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges the output using an internal 50Ω MOSFET connected to VO and PGND. During output discharge operation, the internal low-side MOSFET does not turn on to avoid the possibility of negative voltage at the output.

Current protection

Output over-current protection (OCP) is implemented with a cycle-by-cycle valley detection control circuit. Switch current is monitored by measuring the low-side FET switch voltage between the switch pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, on-time, and output inductance value. This current decreases linearly during the on-time of the low-side FET switch. The average value of the switch current is the load current output. If the measured voltage is higher than the voltage proportional to the current limit, the device continuously monitors the low-side FET switch voltage proportional to the switch current during the low-side turn-on period.

The converter keeps the low-side switch open until the measured voltage falls below the voltage corresponding to the current limit at the end of the switching cycle and the beginning of a new switching cycle. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same way.

There are some important considerations for this overcurrent protection. The load current is half of the inductor peak-to-peak current and is above the overcurrent threshold. Also, when current is limited, the output voltage tends to drop because the required load current may be higher than the converter's available current. This may cause the output undervoltage protection circuit to be activated. When the overcurrent condition is removed, the output voltage will return to the specified value. This protection is non-latching.

Functional Description (continued)

Overvoltage and undervoltage protection

The TPS54325 monitors a resistor-distributed feedback voltage to detect overvoltage and undervoltage. When the feedback voltage is higher than 120% of the target voltage, the OVP comparator output goes high, the circuit locks the high-side MOSFET driver off, and the low-side MOSFET turns on.

When the feedback voltage is lower than 70% of the target voltage, the uvp comparator output goes high and the internal uvp delay counter starts to work. After 250 μs, the device latches onto the internal top and bottom MOSFETs. This feature enables about 1.7 x soft-start time.

UVLO Protection The TPS54325 has under-voltage lockout protection (uvlo) to monitor the voltage at the VREG5 pin. When the VREG5 voltage is below the UVLO threshold voltage, the TPS54325 turns off. This is non-latch protection.

thermal shutdown

The TPS54325 monitors its own temperature. If the temperature exceeds a threshold (usually 150°C), the device is turned off. This is non-latch protection.

Device functional mode

PWM operation

The main control loop of the TPS54325 is an adaptive real-time pulse-width modulation (PWM) controller that supports proprietary D-Cap2 8482 ; mode control. D-Cap2™ mode control combines constant real-time control with internal compensation circuitry for pseudo-fixed frequency and low external component count configurations with low ESR and ceramic output capacitors. It is stable even with almost no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET turns off after the internal one-shot timer expires. This one-shot timer is set by the converter input voltage, VIN, and output voltage VO to maintain a pseudo-fixed frequency over the input voltage range, so it is called adaptive timing control. When the feedback voltage is lower than the reference voltage, a timer is reset and the high-side MOSFET is turned on again. Adds an internal ramp on the reference voltage to simulate output ripple, eliminating the need for ESR-induced output ripple for D-Cap2™ mode control.

PWM frequency and adaptive on-time control

The TPS54325 employs an adaptive real-time control scheme without a dedicated on-board oscillator. The TPS54325 operates at a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time to trigger the timer once. The on-time is inversely proportional to the input voltage and inversely proportional to the output voltage, so the frequency is constant when the duty cycle is VOUT/VIN.

Operation when VIN is less than 4.5 V

It is recommended that the unit be operated with an input voltage higher than 4.5 V. The typical VIN UVLO threshold is 3.7 V, and the device can operate with input voltages below the UVLO voltage. The device does not switch when the input voltage is lower than the actual uvlo voltage. If the en-pin is pulled up externally or left floating, the device will activate when the VIN-pin passes the uvlo threshold. When the slow start sequence is initiated, the handover begins.

Operation with EN control

The enable threshold voltage is 1.6 V (typ). When the en-pin is held below this voltage, the device is disabled and switching is disabled even if the VIN-pin is above the uvlo threshold. In this state, the IC quiescent current decreases. If the en voltage is above the threshold while the VIN pin is above the uvlo threshold, the device will activate. Then enable the toggle and start the slow start sequence.

Functional Description (continued)

Overvoltage and undervoltage protection

The TPS54325 monitors a resistor-distributed feedback voltage to detect overvoltage and undervoltage. When the feedback voltage is higher than 120% of the target voltage, the OVP comparator output goes high, the circuit locks the high-side MOSFET driver off, and the low-side MOSFET turns on.

When the feedback voltage is lower than 70% of the target voltage, the uvp comparator output goes high and the internal uvp delay counter starts to work. After 250µs, the device latches on to the internal top and bottom MOSFETs. This feature enables about 1.7 x soft-start time.

UVLO Protection The TPS54325 has under-voltage lockout protection (uvlo) to monitor the voltage at the VREG5 pin. When the VREG5 voltage is below the UVLO threshold voltage, the TPS54325 turns off. This is non-latch protection.

thermal shutdown

The TPS54325 monitors its own temperature. If the temperature exceeds a threshold (usually 150°C), the device is turned off. This is non-latch protection.

Device functional mode

PWM operation

The main control loop of the TPS54325 is an adaptive real-time pulse width modulation (PWM) controller supporting proprietary D-Cap2™ mode control. D-Cap2™ mode control combines constant real-time control with internal compensation circuitry for pseudo-fixed frequency and low external component count configurations with low ESR and ceramic output capacitors. It is stable even with almost no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET turns off after the internal one-shot timer expires. This one-shot timer is set by the converter input voltage, VIN, and output voltage VO to maintain a pseudo-fixed frequency over the input voltage range, so it is called adaptive timing control. When the feedback voltage is lower than the reference voltage, a timer is reset and the high-side MOSFET is turned on again. Adds an internal ramp on the reference voltage to simulate output ripple, eliminating the need for ESR-induced output ripple for D-Cap2™ mode control.

PWM frequency and adaptive on-time control

The TPS54325 employs an adaptive real-time control scheme without a dedicated on-board oscillator. The TPS54325 operates at a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time to trigger the timer once. The on-time is inversely proportional to the input voltage and inversely proportional to the output voltage, so the frequency is constant when the duty cycle is VOUT/VIN.

Operation when VIN is less than 4.5 V

It is recommended that the unit be operated with an input voltage higher than 4.5 V. The typical VIN UVLO threshold is 3.7 V, and the device can operate with input voltages below the UVLO voltage. The device does not switch when the input voltage is lower than the actual uvlo voltage. If the en-pin is pulled up externally or left floating, the device will activate when the VIN-pin passes the uvlo threshold. When the slow start sequence is initiated, the handover begins.

Operation with EN control

The enable threshold voltage is 1.6 V (typ). When the en-pin is held below this voltage, the device is disabled and switching is disabled even if the VIN-pin is above the uvlo threshold. In this state, the IC quiescent current decreases. If the en voltage is above the threshold while the VIN pin is above the uvlo threshold, the device will activate. Then enable the toggle and start the slow start sequence.

Application and Implementation

Note: The information in the following application sections is not part of the TI component specification and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining the suitability of components for their purpose. Customers should verify and test their design implementation to confirm system functionality.

Application Information

The TPS54325 device is typically used as a buck converter, which converts voltages in the 4.5 V to 18 V range to lower voltages. WebEnch software helps design and analyze circuits.

typical application

Design Example Schematic

Detailed design procedure

Output Voltage Resistor Selection

The output voltage is set by a resistor divider from the output node to the VFB pin. A 1% tolerance or better divider resistor is recommended. Calculate VOUT from Equation 2 and Equation 3. To improve efficiency at very light loads, consider using larger resistor values, too high a resistor will be more susceptible to noise and voltage errors from the VFB input current will be more pronounced.

For output voltages from 0.76 V to 2.5 V:

For output voltages above 2.5 V:

Where • Vout_set = target Vout voltage

Output filter selection

The output filter used with the TPS54325 is an LC circuit. This LC filter has double poles at:

At low frequencies, the overall loop gain is set by the output setpoint resistor divider network and the internal gain of the TPS54325. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain decays at a rate of -40dB per decade and the phase drops rapidly. D-cap2 introduces a high frequency zero, reduces gain attenuation to -20dB per decade, and increases phase to 90 degrees for a decade above zero frequency. The inductors and capacitors chosen for the output filter must be chosen so that the bipolar of Equation 4 is below the high frequency zero, but close enough to provide sufficient phase margin for the stable circuit . To meet this requirement, use the values recommended in Table 2.

optional

For higher output voltages greater than or equal to 1.8 V, additional phase boost can be achieved with a feed-forward capacitor (C4) in parallel with R1.

The peak-to-peak ripple current, peak current, and rms current of the inductor are calculated using Equation 5, Equation 6, and Equation 7. The saturation current rating of the inductor must be greater than the calculated peak current, and the rms or heating current rating must be greater than the calculated rms current.

fsw uses 700 kHz. Make sure the selected inductor is rated for the peak current in Equation 6 and the rms current in Equation 7.

In this design example, the calculated peak current is 3.47A and the calculated rms current is 3.01A. The inductor used was a TDK SPM6530-1R5M100 with a peak current rating of 11.5A and an rms current rating of 11A.

Capacitor value and ESR determine the amount of output voltage ripple. The TPS54325 is suitable for ceramic or other low ESR capacitors. The recommended range of values is 22 microF to 68 microF. Use Equation 8 to determine the required rms current rating of the output capacitor.

This design uses two TDK C3216x5r0J226M 22-µF output capacitors. Typical ESR is 2 MΩ. The calculated rms current is 0.271 A, and each output capacitor is rated at 4 A.

Input Capacitor Selection

The TPS54325 requires an input decoupling capacitor and, depending on the application, a bulk capacitor. For decoupling capacitors, ceramic capacitors above 10 mF are recommended. It is recommended to add a 0.1-µF capacitor between pin 14 and ground to improve the stability of the overcurrent limit function. The voltage rating of the capacitor must be greater than the maximum input voltage.

Bootstrap capacitor selection A 0.1µF ceramic capacitor must be connected between the VBST to SW pins for proper operation. Ceramic capacitors are recommended.

Power Recommendations

The device is designed to operate over an input voltage range of 4.5 V to 18 V. This input supply should be well regulated. If the input supply is more than a few inches away from the converter, additional bulk capacitors may be required in addition to ceramic bypass capacitors. A 100µF electrolytic capacitor is a typical choice.

layout

Layout Guidelines 1. Keep the input switch current loop as small as possible. 2. Keep the sw node as small and short as possible to minimize parasitic capacitance and inductance, and to minimize radiated emissions. The Kelvin connection should go from the output to the feedback pin of the device. three. Keep analog and non-switching elements away from switching elements. 4. Make a single point connection from signal ground to power ground. 5. Switching current is not allowed to flow under the device. 6. Maintain pattern line widths for VIN and PGND. 7. The exposed pad of the device must be soldered to PGND. 8. The VREG5 capacitor should be placed near the device and connected to PGND. 9. The output capacitor should be connected to the broad pgnd mode. 10. The voltage feedback loop should be as short as possible, preferably with a grounded shield. 11. The lower resistor of the voltage divider connected to the VFB pin should be connected to SGND. 12. It is best to provide enough VIA for VIN, SW, and PGND connections. 13. The printed circuit board pattern for VIN, SW, and PGND should be as wide as possible. 14. If VIN and VCC are shorted, VIN and VCC mode need to be connected with wide mode lines. 15. The VIN capacitor should be as close as possible to the device.

layout example

Thermal factor

This PowerPad™ pack contains an exposed thermal pad designed to attach to an external heat sink. The thermal pad must be soldered directly to the Printed Board (PCB). After soldering, the printed circuit board can be used as a heat sink. Additionally, through the use of thermal vias, the thermal pads can be connected directly to the appropriate copper planes as shown in the electrical schematic of the device, or they can be connected to special thermal structures designed into the PCB. The design optimizes heat transfer from integrated circuits (ICs).

For more information on the PowerPad™ software package and how to take advantage of its cooling capabilities, see: • PowerPad™ made easy (SLMA004). • PowerPad™ Thermal Enhancement Package (SLMA002).

Device and Documentation Support

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constitutes an endorsement of the suitability of such products or services, or a warranty, representation or endorsement of such products or services alone or in combination with any TI product or service.

development support

RELATED DOCUMENTS • Soldering Absolute Maximum Ratings (snoa549). • PowerPad™ is easy to use (SLMA004). • PowerPad™ Thermal Enhancement Package (SLMA002). • Thermal measurement of semiconductor and integrated circuit packages (SPRA953).

The trademarks D-Cap2, PowerPad are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc. All other trademarks are the property of their respective owners. 12.4 ESD precautions

These devices have limited built-in ESD protection. During storage or handling, the wires should be shorted together or placed in conductive foam to prevent electrostatic damage to the MOS gate.

SLYZ022-TI Glossary. This glossary lists and explains terms, abbreviations and definitions.