The C8051F320 MCU features an onboard Universal Serial Bus (USB) 2.0 functional controller that integrates a transceiver and on-chip clock recovery. USB applications do not require external resistors, crystals, voltage regulators, EEPROM or other components. The MCU includes a powerful 8051 core with 25 MHz performance and 16 kB Flash, 2.25 kB RAM. On-chip analog functions include 10-bit, 17-channel, 200 ksps ADC, voltage reference, ±1.5 internal oscillator, 2 comparators and temperature sensor. The C8051F320 integrates additional communication interfaces and rich analog in a 7x7 mm, QFP32, providing a true single-chip solution for embedded USB applications.

The C8051F320/1 device is a fully integrated mixed-signal system-on-chip. The outstanding features are:

High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)

In-system, full-speed, non-intrusive debug interface (on-chip)

Universal Serial Bus (USB) functional controller with eight flexible endpoint pipes, integrated transceiver and 1k FIFO RAM

Supply Voltage Regulator (5 to 3 V)

True 10-bit 200 ksps 17-channel single-ended/differential ADC with analog multiplexer

On-chip voltage reference and temperature sensor

On-chip voltage comparators (2)

Precision programmable 12 MHz internal oscillator and 4x clock multiplier

16 kB on-chip flash

2304 bytes of on-chip RAM (256 + 1k + 1k USB FIFO)

SMBus/I2C, enhanced UART and enhanced SPI serial interfaces, implemented in hardware

Four general-purpose 16-bit timers

Programmable Counter/Timer Array (PCA) with Five Capture/Compare Modules and Watchdog Timer Function

On-chip power-on reset, VDD monitor and missing clock detector

25/21 port I/O (5 V tolerance)

With on-chip power-on reset, VDD monitor, voltage regulator, watchdog timer and clock oscillator, the C8051F320/1 device is a true stand-alone system-on-chip solution. The flash memory can be reprogrammed online, providing non-volatile data storage and also allowing field upgrades of the 8051 firmware. User software has full control of all peripherals and can individually shut down any or all peripherals to save power.

The on-chip Silicon Labs 2-wire (C2) development interface allows non-intrusive (without using on-chip resources), full-speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspecting and modifying memory and registers, setting breakpoints, single step, run and pause commands. When debugging, all analog and digital peripherals are fully functional

Use C2. Two C2 interface pins can be shared with user functions, allowing package pins to be freed during system debugging. Each device has an operating temperature range of 2.7 to 3.6 V and an operating temperature range of -40 to +85°C. (Note that 3.0 to 3.6 V is required for USB communication.) The port I/O and /RST pins can tolerate input signals up to 5 V. The C8051F320/1 is available in a 32-pin LQFP or 28-pin QFN package.

C8051F320 block diagram

C8051F321 block diagram

The C8051F320/1 series features Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; software can be developed using standard 803x/805x assemblers and compilers. The CIP-51 core provides all the peripherals that come with the standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 2304 bytes of on-chip RAM, ?? 128 bytes of Special Function Register (SFR) address space and 25/21 I/O pins.

Increase throughput:

The CIP-51 adopts a pipelined architecture, which greatly improves the instruction throughput compared to the standard 8051 architecture. In the standard 8051, all instructions except MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz. In contrast, the CIP-51 core executes 70% of the instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. CIP-51 has a total of 109 instructions. The following table shows the total number of instructions required for each execution time.

Additional features:

The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve end-application performance and ease of use. The extended interrupt handler provides 16 interrupt sources for the CIP-51 (compared to 7 for the standard 8051), allowing a large number of analog and digital peripheral interrupt controllers. Interrupt-driven systems require less MCU intervention, providing more efficient throughput. Additional Interrupts Source code is very useful when building multitasking real-time systems. Provides 9 reset sources: power-on reset circuit (POR), on-chip VDD monitor (forced reset) when supply voltage falls below VRST (as shown in Table 10.1 on page 105), USB controller (USB bus reset or VBUS Conversion), Watchdog Timer, Missing Clock Detector, Voltage Level Detection of Comparator0, Forced Software Reset, External Reset Pin and Error Flash Read/Write Protection Circuit. Except for POR, reset input pin or flash error, each reset source can be disabled by the user in software. During power-on reset, the WDT can be permanently enabled in software. The internal oscillator is factory calibrated to 12 MHz ±1.5%, and the internal oscillator period can be user-programmed in ~0.25% increments. The clock recovery mechanism allows the use of the internal oscillator 4x clock multiplier as the USB clock source in full-speed mode; the internal oscillator can also be used as the USB clock source in low-speed mode. An external oscillator can also be used with the 4x clock multiplier. Also includes an external oscillator drive circuit that allows an external crystal, ceramic resonator, capacitor, RC or CMOS clock source to generate the system clock. The system clock can be configured to use the internal oscillator, the external oscillator or the clock multiplier output divided by 2. If desired,

The system clock source can be switched between oscillator sources on the fly. An external oscillator can be very useful in low power applications, allowing the MCU to run from a slow (power saving) external clock source while periodically switching to the internal oscillator as needed.

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM with the upper 128 bytes double mapped. Indirect addressing accesses the general upper 128 bytes of destination RAM and direct addressing accesses the 128 bytes SFR address space. lower 128 bytes

RAM can be accessed through direct and indirect addressing. The first 32 bytes can be addressed as four banks of general purpose registers, the next 16 bytes can be byte-addressable or bit-addressable. The program memory consists of 16 kB Flash. The memory can reprogram sectors within a 512-byte system, requiring no special off-chip programming voltages. See the figure below for the MCU system memory map.

The Universal Serial Bus controller (USB0) is a USB 2.0 compliant full-speed or low-speed function with an integrated transceiver and endpoint FIFO RAM. There are eight endpoint pipes in total: a bidirectional pipe control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints 1-3 IN/OUT). A 1k block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed between endpoints 0-3; endpoints 1-3 FIFO slots can be configured as IN, OUT or IN and OUT (split mode). The maximum FIFO size is 512 bytes (Endpoint3). USB0 can operate as a full-speed or low-speed function. On-chip 4x clock multiplier and clock recovery circuitry allow full-speed and low-speed options using the on-chip precision oscillator. USB clock source. An external oscillator source can also be used with the 4x clock multiplier to generate the USB clock. The CPU clock source has nothing to do with the USB clock.

The USB transceiver is compliant with the USB 2.0 standard and includes on-chip termination and pull-up resistors. The pull-up resistors can be enabled/disabled by software and displayed on the D+ or D- pins depending on the software-selected speed setting (full or low speed).

Voltage Regulator

The C8051F320/1 device includes a 5 to 3 V regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 software can be enabled/disabled.

The C8051F320/1 device includes on-chip Silicon Labs 2-wire (C2) debug circuitry that provides non-intrusive, full-speed, in-circuit debugging of production parts installed in the end application. Silicon Labs' debug system supports inspection and modification of memory and registers, breakpoints and single stepping. No additional target RAM, program memory, timers or communication channels are required. All digital and analog peripherals are functional and will work when debugging. All peripherals (except USB, ADC and SMBus) are stopped when the MCU is halted, single-stepped, or at a breakpoint, to maintain synchronization.

The C8051F320DK Development Kit provides all the hardware and software required to develop application code and in-circuit debugging with the C8051F320/1 MCU. The kit includes a software developer's studio and debugger with software, 8051 assembler and linker, evaluation 'C' compiler and debug adapter. It also has a target application board with the C8051F320 MCU installed, which is required to connect the cables to the PC and wall-mounted power supply. The development kit content can also be used to program and debug the device on the production PCB using the corresponding connections to the programming pins. Compared to the lab, the Silicon Labs IDE interface is a very superior development and debug configuration standard MCU emulator, using the on-board "ICE chip" and requiring the MCU in the application board.

Development/in-system debugging diagram

C8051F320 devices include 25 I/O pins (3 byte-wide ports and one 1-bit wide port); C8051F321 devices include 21 I/O pins (two byte-wide ports, one 4-bit wide port) wide port and a 1-bit wide port). Should

The C8051F320/1 port behaves like a typical 8051 port with some enhancements. Each port pin can be configured as an analog input or as a digital I/O pin. Pins selected as digital I/Os can additionally be configured as push-pull or open-drain outputs. The "weak pull-ups" fixed on typical 8051 devices may be disabled globally, providing power-saving features. A digital crossbar allows mapping of internal digital system resources to port I/O pins (see diagram below). On-chip counters/timers, serial buses, HW interrupts, comparator outputs, and other digital signal controllers can be configured to appear on port I/O pins specified in the crossbar control register. This allows the user to select the exact combination of general purpose port I/O and digital resources required for a particular application.

The C8051F320/1 series includes SMBus/I2C interface, full-duplex UART configuration with enhanced baud rate and enhanced SPI interface. Each serial bus is fully implemented in hardware and uses CIP-51's interrupts extensively, so very little CPU intervention is required.

1.8. The programmable counter array includes the on-chip programmable counter/timer array (PCA) in addition to four 16-bit general-purpose counters/timers. The PCA consists of a dedicated 16-bit counter/timer time base and five programmable capture/compare modules. The PCA clock is derived from one of six sources: system clock divided by 12, system clock divided by 4, timer 0 overflow, external clock input (ECI), system clock or external oscillator clock source divided by 8. External clock source selection Very useful for real-time clock functions, where the PCA is clocked by an external source and the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, software timer, high-speed output, 8- or 16-bit pulse width modulator, or frequency output. Additionally, Capture/Compare Module 4 provides a Watchdog Timer (WDT) function. After a system reset, module 4 is configured and enabled in WDT mode. PCA capture/compare module I/Os and external clock inputs can be routed to port I/Os through digital crossbar switches.

The C8051F320/1 device includes an on-chip 10-bit SAR ADC and a 17-channel differential input multiplexer. The ADC has a maximum throughput of 200 ksps and offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer with selectable positive and negative ADC inputs. Ports1-3 can be used as ADC inputs; in addition, the on-chip temperature sensor outputs and

The supply voltage (VDD) can be used as ADC input. User firmware may turn off the ADC to conserve power. Conversions can be initiated in six ways: software command, overflow of timers 0, 1, 2 or 3, or an external conversion start signal. This flexibility allows software to trigger the start event of a conversion, a periodic signal (timer overflow) or an external HW signal. Indicates conversion completion via status bits and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFR after the conversion is complete. The Window Compare register for ADC data can be configured to interrupt the controller when ADC data is within or outside the specified range. The ADC can continuously monitor critical voltages in background mode without interrupting the controller unless the converted data is within/outside of the specified range.

The C8051F320/1 device includes two on-chip voltage comparators that can be enabled/disabled and configured by user software. Port I/O pins can be configured as comparator inputs by selecting the multiplexer. If desired, two comparator outputs can be routed to port pins: a latched output and/or an unlocked (asynchronous) output. The comparator response time is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hysteresis is also configurable. Comparator interrupts can be generated on rising, falling, or both edges. In idle mode, these interrupts can be used as "wake-up" sources. Comparator 0 can also be configured as a reset source. The following figure shows the Comparator0 block diagram