The CMOS BQ2201SN SRAM non-volatile controller unit provides all the functions necessary to convert standard CMOS SRAM into non-volatile read/write memory. Precision comparators monitor the 5V VCC input for out-of-tolerance conditions. When out of tolerance is detected, the conditional chip enable output is forced inactive to write protect any standard CMOS SRAM. During a power failure, the external SRAM switches from VCC for one of the two 3V backup supplies. On subsequent power-ups, the SRAM is write-protected until a power-valid condition exists. The bq2201 features footprint and timing compatible industry standards with the added benefit of chip-enable propagation delays of less than 10ns.

feature

Power monitoring and switching for 3V battery backup applications

Write Protect Controls

3 volt main battery input

Chip Enable Less than 10ns Propagation Delay

5% or 10% supply operations

Pin Connection Diagram

pin name

VOUT power output

BC1-BC2 3V main backup battery input

THS Threshold Select Input

CE Chip Enable Active Low Input

CECON Condition Chip Enable Output

VCC + 5V power input

VSS ground

NC no connection

Function description, pin connection:

External CMOS static RAM can be battery powered using VOUT and conditional chip enable outputs from the bq2201 pins. As VCC fails to cool down during power, the conditional chip-enable output CECON is forced inactive, independent of the chip-enable input CE. This activity unconditionally write protects the external SRAM as VCC from falling outside the tolerance threshold VPFD. VPFD is selected by the threshold select input pin THS.

If THS is associated with VSS, power failure detection occurs at 4.62V typical 5% supply operation. If THS is tied to VCC, power failure detection occurs at 4.37V typical for 10% supply operation. The THS pin must be connected to VSS or VCC for proper operation. If a memory access is in progress during power failure detection, the memory cycle will continue to complete the memory is write-protected. If the memory cycle does not expire within time tWPT, the CECON output is unconditionally driven high, writing-protected the memory.

As the supply continues to drop beyond VPFD, the internal switching device forces VOUT to one of the two external backup energy sources. VEC keeps CECON at a high energy source.

During power-up, when VCC rises above the backup battery input voltage, VOUT switches back to the VCC supply to source VOUT. The CECON output remains inactive for the time tCER (120 ms maximum) after reaching VPFD, independent of the CE input, allowing the processor to stabilize.

During power-active operation, the CE input is fed through a propagation delay of less than 10ns to the CECON output. Non-volatile is a hookup implemented in hardware, as shown in the figure above. Energy Cell Inputs - BC1, BC2 provide two primary backup energy inputs on the bq2201. The BC1 and BC2 inputs accept 3V primary cells, usually some type of lithium chemistry. If no primary cell is used on BC1 or BC2, the unused inputs should be bound to VSS. If using two inputs, use VOUT during power failure

The output is only fed by BC1 as long as it is greater than 2.5V. If the voltage of BC1 is lower than 2.5V, the internal voltage isolation switch automatically switches VOUT from BC1 to BC2. To prevent battery drain retention when there is no valid data, VOUT and CECON are internally isolated

BC1 and BC2 by either: the battery is initially connected to BC1 or BC2, or by displaying an isolated signal on CE.

When VCC crosses, an effective isolation signal requires CE to be low for both VPFD and VSO during power down. See below. Between these two time points, CE must be brought to (0.48 to 0.52)*VCC for at least 700ns. If CE exceeds, the isolated signal is inactive at 0.54 * VCCVSO at any point between VCC crossing VPFD and . Appropriate battery connected to VOUT and CECON

Apply now and cancel the VCC.

Continuation diagram when power off

Power-on sequence diagram