Features

DESCRIPTION The TPS54160A device is a 60-V, 1.5-A, step-down 1.3.5 V to 60 V input voltage range regulator with an integrated high-side MOSFET. 200-MΩ high-side MOSFET current-mode control provides simple external high efficiency at light loads, pulse compensation and flexible component selection. Skip ECO Mode™ Low Ripple Pulse Skip Mode reduces no-load, regulated output supply current to 116 μA. Using the TPS54160A with a tighter enable threshold than the enable pin, the shutdown supply current is reduced to 1.3TPS54160 for a more accurate uvlo voltage μA. Adjustable UVLO voltage and hysteresis under voltage lock are internal. Set to 2.5 V, but using the enable pin increases the 116µA operating quiescent current. The output μA shutdown current voltage startup ramp is controlled by a slow-start 100 kHz to 2.5 MHz switching frequency pin, which is also configurable for sequencing/tracking. Open-drain power-good synchronization with an external clock signal indicates that the output is within 94% to 107% of its rated voltage for adjustable slow-start/sequencing. Good UV and OV power output, wide switching frequency range, optimized efficiency 0.8-V internal reference voltage and external component size. MSOP10 and 3MM x 3MM VSON packages with frequency folding back and thermal shutdown to protect PowerPad™ parts from overload conditions. By Webbench and SwitcherPro Device Information Software Tool Order Number Package (PIN) Body Dimensions TPS54160DGQ2 Application MSOP (10) 3mm x 3mm TPS54160ADGQ 12-V, 24-V and 48-V Industrial and Commercial TPS54160ADRC VSON (10) 3mm x 3mm low power system supports aftermarket auto accessories: video, GPS, entertainment

Detailed Description
The TPS54160A device is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control that reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100kHz to 2500kHz enables efficiency and size optimization when selecting output filter components. Use a resistor to ground on the RT/CLK pin to adjust the switching frequency. The device has an internal Phase Locked Loop (PLL) on the RT/CLK pin to synchronize the power switch on to the falling edge of the external system clock.
The default startup voltage of the TPS54160A is approximately 2.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. Additionally, the pull-up current provides default conditions. When the en-pin is floating, the device operates. The operating current is 116μA when not switching and no load. When the device is disabled, the supply current is 1.3µA. The integrated 200MΩ high-side MOSFET allows high-efficiency power supply designs capable of delivering 1.5 A of continuous current to the load. The TPS54160A reduces external part count by integrating a bootstrap charge diode. Biasing of the integrated high-side MOSFET is provided by a start-up capacitor on the ph pin. The startup capacitor voltage is monitored by a UVLO circuit, and when the startup voltage falls below a preset threshold, the startup high-side MOSFET turns off. The TPS54160A can operate at high duty cycles because the UVLO is activated. The output voltage can be reduced to a minimum value of 0.8V reference voltage.
The TPS54160A has a power good comparator (PWRGD) that asserts when the regulated output voltage is less than 92% or greater than 109% of the rated output voltage. The pwrgd pin is an open-drain output that opens when the Vsense pin voltage is between 94% and 107% of the rated output voltage, allowing the pin to transition to a high voltage when a pull-up resistor is used.
The TPS54160A utilizes an OV power good comparator to minimize excessive output overvoltage (OV) transients. When the OV comparator is activated, the high-side MOSFET is turned off and shielded until the output voltage falls below 107%.
The SS/TR (Slow Start/Track) pin is used to minimize inrush current or provide power sequencing during power up. A small value capacitor should be coupled to the pin to adjust for slow start-up time. Resistor dividers can be connected to the pins to meet critical power sequencing requirements. The SS/TR pin is discharged before the output is powered up. This discharge ensures repeatable restarts after overtemperature faults, uvlo faults, or disabled states.
The TPS54160A also discharges the slow-start capacitor under overload conditions through an overload recovery circuit. Once the fault condition is removed, the overload recovery circuit will slowly start the output from the fault voltage to the rated regulated voltage. A frequency folding circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current.

Function description Fixed frequency PWM control
The TPS54160A uses adjustable fixed frequency, peak current mode control. The output voltage is compared to an internal voltage reference provided by an error amplifier driving the comp pin through an external resistor on the Vsense pin. An internal oscillator activates the high-side power switch. Compare the error amplifier output to the high-side power switch current. When the power switch current reaches the level set by the compensation voltage, the power switch is turned off. As the output current increases and decreases, the compensation pin voltage will increase and decrease. The device implements current limiting by limiting the compensation pin voltage to a maximum level. ECO Mode™ is achieved using minimal clamps on the compressor pins.
Slope Compensation Output Current
The TPS54160A adds a compensation ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the entire duty cycle range.
Pulse Skip ECO Mode The TPS54160A enters pulse skip mode when the voltage on the comp pin is at the minimum clamp value. The TPS54160A operates in pulse-skipping mode at light load currents to improve efficiency. The peak switch current during pulse skip mode will be the larger of 50mA or peak inductor current, which is a function of minimum on-time, input voltage, output voltage and inductor value. When the load current is low and the output voltage is within specification, the device will enter sleep mode, drawing only 116µA of input.

Characterization (continued) Quiescent current. When the device is in sleep mode, the output power is provided by the output capacitor. As the load current decreases, the time the output capacitor supplies the load current increases and the switching frequency decreases, reducing gate drive and switching losses. When the output voltage drops, the TPS54160A wakes up from sleep mode, the power switch is turned on to charge the output capacitor, and the internal PLL remains active during sleep mode. In pulse skipping mode, switching transitions occur synchronously with an external clock signal when operating at light load currents.
Pulse-skipping mode operation conduction voltage (bootstrap)
The TPS54160A has an integrated startup regulator that requires a small ceramic capacitor between the startup and ph pins to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1µF. Due to the stable temperature and voltage characteristics, it is recommended to use ceramic capacitors with X7R or X5R grade dielectrics. To improve the voltage drop, the TPS54160A is designed to operate at 100% duty cycle as long as the startup to ph pin voltage is greater than 2.1 V. When the startup-to-ph voltage drops below 2.1 V, the high-side MOSFET is turned off using a UVLO circuit that allows the low-side diode to conduct, which allows the startup capacitor to be refreshed. Since the supply current from the startup capacitor is lower, the high-side MOSFET can remain on for more switching cycles than it refreshes, and therefore, the effective duty cycle limit due to the startup regulator system is higher.
Low Dropout Operation The duty cycle of the regulator during dropout is primarily determined by the voltage drop across the power MOSFETs, inductors, low-side diodes, and printed circuit board resistors. Under input voltage drop operating conditions, the high-side MOSFET can maintain 100% duty cycle to maintain output regulation or until the bootstrap ph voltage drops below 2.1 V.
Once the high side is turned off, the low side diode will conduct and the boot capacitor will recharge. During this startup capacitor charging time, the inductor current will drop until the high-side MOSFET turns on. The charging time is longer than the typical high-side turn-off time of previous switching cycles, so the inductor current ripple is larger, resulting in a larger output ripple voltage. The charging time is a function of the input voltage, the value of the startup capacitor, and the impedance of the internal startup charging diode.
It is important to note that in the absence of load current, the maximum duty cycle is applied for a longer period of time. In applications where the input and output voltages differ by less than 3V, when the voltage across the bootstrap capacitor falls below the 2.1V threshold, the high-side MOSFET will turn off, but there is not enough current in the inductor to pull down the ph pin to give the bootstrap capacitor Charge. The regulator will not switch because the startup capacitor is less than 2.1V and the output capacitor will decay until the difference between the input voltage and the output voltage is 2.1V. At this point, the startup undervoltage lockout is exceeded and the device will switch until the desired output voltage is reached.

CHARACTERISTICS (continued) Voltage is proportional to load current. Startup voltage is defined as the input voltage required to regulate the output within 1%. The stop voltage is the input voltage when the output voltage drops by 5% or when the switching is stopped.
Error amplifier

The TPS54160A has a transconductance amplifier for the error amplifier. The error amplifier compares the Vsense voltage to the lower of the ss/tr pin voltage or the internal 0.8 volt reference. In normal operation, the transconductance (gm) of the error amplifier is 97 μA/V. In slow-start operation, the transconductance is only a fraction of the normal operating transconductance. When the voltage at the Vsense pin is below 0.8V and the device is regulated using the SS/TR voltage, the transconductance is 26µA/V. Frequency compensation components (capacitors, series resistors and capacitors) are added to the comp pin to ground.
Voltage Reference The voltage reference system produces an accurate ±2% temperature reference voltage by scaling the output of a temperature-stabilized bandgap circuit.
Adjusting the Output Voltage The output voltage is set through a resistor divider from the output node to the Vsense pin. A 1% tolerance or better divider resistor is recommended. Start with a 10 kΩ resistor for R2 and use Equation 1 to calculate R1. To improve efficiency at light loads, consider using larger resistor values. If this value is too high, the regulator will be more susceptible to noise and voltage errors from the Vsense input current can be noticed.
Enabling and Adjusting Undervoltage Lockout The TPS54160A will be disabled when the VIN pin voltage is below 2.5 V. If the application requires higher undervoltage lockout (uvlo), use the en pin shown in Figure 29 to adjust the input voltage uvlo by using two external resistors. Although it is not required to use the uvlo trim register, it is strongly recommended to provide consistent power-up behavior when operating. The EN pin has an internal pull-up current source I1 of 0.9µA, which provides the default condition for the TPS54160A to operate when the EN pin is floating. Once the en-pin voltage exceeds 1.25V, an additional 2.9µA of hysteresis is added, ihys. This additional current contributes to the input voltage hysteresis. Use Equation 2 to set the external hysteresis of the input voltage. Use Equation 3 to set the input start voltage.

CHARACTERISTICS (CONTINUED) 8.3.10 Slow Start and Tracking Pins (SS/TR)
The TPS54160A effectively uses the internal reference voltage or the lower of the SS/TR pin voltage as the reference for the power supply and regulates the output accordingly. A capacitor on the SS/TR pin to ground achieves a slow start-up time. The TPS54160A has an internal pull-up current source of 2µA that charges the external slow-start capacitor. The slow start time (10% to 90%) is calculated as shown in Equation 6. The reference voltage (Vref) is 0.8V and the slow start current (ISS) is 2µA. The slow-start capacitor should be kept below 0.47µF and greater than 0.47nF.
On power-up, the TPS54160A does not start switching until the slow-start pin discharges below 40 mV to ensure normal power-up, see Figure 32.
Additionally, during normal operation, the TPS54160A stops switching and SS/TR must discharge to 40 mV when the voltage at the VIN pin falls below VIN UVLO, the EN pin falls below 1.25 V, or a thermal shutdown event occurs.
The Vsense voltage follows the SS/TR pin voltage with a 45 mV offset of up to 85% of the internal voltage reference. When the ss/tr voltage on the internal reference voltage is greater than 85%, the offset increases as the effective system reference voltage transitions from the ss/tr voltage to the internal reference voltage (see Figure 24). The SS/TR voltage rises linearly until clamped at 1.7 V.
Overload recovery circuit for operation of SS/TR pin at startup
The TPS54160A has overload recovery (OLR) circuitry. Once the fault condition is removed, the OLR circuit will output from the overload voltage to the rated regulated voltage. When the error amplifier goes from a fault state to a high voltage, the OLR circuit uses an internal pull-down of 100µA to discharge the SS/TR pin to a voltage slightly higher than the Vsense pin voltage. When the fault condition is removed, the output slows from the fault voltage to the rated output voltage.

Characterization (continued)
Many common power sequencing methods can be implemented using the ss/tr, en, and pwrgd pins. The sequential approach can be implemented using the open-drain output of the power reset pin on the other device. The sequential method using two TPS54160A devices is shown in Figure 33. Power good is connected to the EN pin on the TPS54160A, and once the main power supply reaches the specified value, the second power supply can be enabled. A 1nF ceramic capacitor on the en pin of the second power supply provides a 1ms startup delay if required.

Ratiometric and Simultaneous Startup Sequencing The R1 and R2 resistor network shown in the schematic is connected to the output of a power supply or other voltage reference source that needs to be tracked, enabling ratiometric measurement and synchronizing power supply sequencing. Using Equation 7 and Equation 8, the tracking resistance can be calculated to turn on VOUT2 a little earlier, later, or at the same time as VOUT1. Equation 9 is the voltage difference between VOUT1 and VOUT2 at 95% of rated output regulation. When sequencing simultaneously, the ΔV variable is zero volts. In order to minimize the effect of ss/tr on the vsense offset (vss(offset)) inherent in the slow-start circuit and the offset produced by the pull-up current source (iss) and the tracking resistor, vss(offset) and iss are used as variables included in the equation. To design a ratiometric startup where the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number for ΔV in Equations 7 through 9. Equation 9 yields a positive number for applications where VOUT2 is slightly lower than VOUT1 for regulation. Since the SS/TR pin must be pulled below 40 mV before startup after an EN, UVLO, or thermal shutdown fault, careful selection of the tracking resistor is required to ensure that the device restarts after a fault. Make sure that the value of R1 calculated in Equation 7 is greater than the value calculated in Equation 10 to ensure that the device can recover from the failure. When the SS/TR voltage exceeds 85% of the rated reference voltage, the vss (offset) becomes larger as the slow-start circuit gradually switches the regulated reference to the internal reference voltage. SS/TR pin voltage needs to be greater than 1.3 V to fully switch to internal voltage reference

Characterization (continued) Constant Switching Frequency and Timing Resistors (RT/CLK Pins)
The switching frequency of the TPS54160A can be adjusted from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and there must be a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 41 or Figure 42. To reduce the size of the solution, the switching frequency is usually set as high as possible, but the trade-off of power efficiency, maximum input voltage, and minimum controllable on-time should be considered.
The minimum controllable turn-on time is typically 130ns and limits the maximum operating input voltage.
High frequency range Low frequency band overcurrent protection and frequency shifting
The TPS54160A performs current-mode control that uses the compensation pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. The switch current and the compensation pin voltage are compared each cycle, and when the peak switch current crosses the compensation voltage, the high-side switch is turned off. During an overcurrent condition that pulls the output voltage low, the error amplifier responds by driving the comp pin high, increasing the switch current. The output of the error amplifier is fixed internally and acts as a switch current limiter.
To increase the maximum operating switching frequency at high input voltages, the TPS54160A implements a frequency offset. The switching frequency is divided by 8, 4, 2, and 1, and voltages from 0 to 0.8 volts are on the Vsense pin.
The device implements digital frequency shifting for synchronization with an external clock under normal startup and fault conditions. Since the unit can only divide the switching frequency by 8, there is a maximum input voltage limit at which the unit operates and still has frequency shift protection.
During a short circuit event (especially in high input voltage applications), the control loop has a finite minimum controllable on-time, while the output has a low voltage. During the switch on-time, the inductor current can rise to the peak current limit due to the high input voltage and short on-time. During the switch off time, the inductor typically does not have enough off time and the output voltage to ramp the inductor down by the ramp up amount. The frequency shift effectively increases the off time, allowing the current to drop.

Characterization (continued) Selecting the switching frequency The switching frequency selected should be the lower of the two equations (Equation 12 and Equation 13). Equation 12 is the maximum switching frequency limit set by the minimum controllable on-time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short-circuit protection at high input voltages, the switching frequency should be set less than the fsw (maxshift) frequency. In Equation 13, to calculate the maximum switching frequency, the integer fdiv is increased from 1 to 8, corresponding to the frequency shift, considering that the output voltage is reduced from the rated voltage to 0 V.
In Figure 43, the solid line illustrates a typical safe operating region for frequency offset, assuming an output voltage of 0 V, an inductor resistance of 0.1 Ω, a FET on-resistance of 0.2 Ω, and a diode drop of 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations into a spreadsheet or other software, or use switcherpro design software to determine the switching frequency.

Functional Description (continued) How to connect RT/CLK pins
The RT/CLK pin can be used to synchronize the regulator to an external system clock. The circuit network connects the square wave to the RT/CLK pin. The square wave amplitude must transition to values below 0.5 V and above 2.2 V on the RT/CLK pin with an on time greater than 40 ns and an off time greater than 40 ns. The sync frequency range is 300 kHz to 2200 kHz. The rising edge of ph is synchronized with the falling edge of the rt/clk pin signal. The design of the external synchronization circuit should ensure that when the synchronization signal is turned off, the device has a default frequency setting resistor connected from the RT/CLK pin to ground. It is recommended to use a frequency setting resistor with a 50Ω resistor to ground as shown in Figure 44. The resistors should set the switching frequency close to the external CLK frequency. It is recommended to AC-couple the sync signal to the RT/CLK pin and a 4KΩ series resistor through a 10 pF ceramic capacitor. The series resistor reduces pH jitter in heavy-load applications when synchronizing to an external clock, and in applications transitioning from synchronous mode to RT mode. The first time CLK is pulled above the CLK threshold, the device switches from RT resistor frequency to PLL mode. When the PLL begins to lock to the external signal, the internal 0.5V voltage source is removed and the CLK pin becomes high impedance. Since there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set by the external resistor. The device transitions from resistive mode to PLL mode and will then increase or decrease the switching frequency until the PLL locks to the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistive mode, the switching frequency will be reduced from the CLK frequency to 150 kHz, then 0.5 V will be reapplied and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1, and voltages from 0 to 0.8 volts are on the Vsense pin. The device implements digital frequency shifting for synchronization with an external clock under normal startup and fault conditions.

CHARACTERISTICS (CONTINUED) OVERVOLTAGE TRANSIENT PROTECTION
The TPS54160A integrates an over-voltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or during strong unloading transients on power supply designs with low value output capacitors. For example, when the output of the power supply is overloaded, the error amplifier compares the actual output voltage to an internal reference voltage. If the VSENSE pin voltage falls below the internal reference voltage for an extended period of time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Therefore, the maximum output current is requested. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage responds faster than the error amplifier output, resulting in the possibility of output overshoot. When using low value output capacitors, the OVTP function minimizes output overshoot by implementing circuitry to compare the Vsense pin voltage to the OVTP threshold of 109% of the internal reference voltage. If the Vsense pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled to prevent current flow into the output and minimize output overshoot. When the voltage falls below the OVTP threshold, the high-side MOSFET can be turned on on the next clock cycle.
Thermal Shutdown When the junction temperature exceeds 182°C, the device performs an internal thermal shutdown to protect itself. Thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the mold temperature drops below 182°C, the device restarts the power-up sequence by releasing the SS/TR pin.
8.3.20 Small Signal Model of Loop Response
Equivalent model of the TPS54160A control loop that can be modeled in a circuit simulation program to examine frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a GMEA of 97µA/V. The error amplifier can be modeled with an ideal voltage-controlled current source. Resistive reaction and capacitor together simulate the open-loop gain and frequency response of an amplifier. A 1mV AC voltage source between nodes A and B effectively blocks the control loop of frequency response measurement. Figure C/A shows the frequency compensated small signal response. Figures A/B show the small signal response of the entire loop. In a time domain analysis, the dynamic loop response can be examined by replacing RL with a current source with appropriate load step amplitude and step rate. This equivalent model applies only to continuous conduction mode designs.

Layout Guidelines Layout is a critical part of good power supply design. There are several signal paths that can conduct rapidly changing currents or voltages that can interact with stray inductance or capacitance to create noise or degrade power supply performance. 8226 ; To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor (with X5R or X7R dielectric). • Care should be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the capture diode anode. • The ground pin should be tied directly to the power strip below the device and power strip. • The power board should be connected to any internal PCB ground plane using multiple vias directly under the device. • The ph pin should be connected to the cathode of the capture diode and the output inductor. • Since the ph connection is the switch node, the capture diode and output inductance are placed close to the ph pin and the area of the PCB conductors is minimized to prevent excessive capacitive coupling. • For full load operation, the top floor area must provide an adequate cooling area. • The RT/CLK pins are sensitive to noise, so the RT resistors should be placed as close as possible to the device and routed with a minimum trace length. • Additional external components can be placed approximately as shown. • Acceptable performance can be obtained with an alternate PCB layout that has shown good results and is used as a guideline.
layout example