Inside the CAT25640VI-GT3 is an EEPROM serial 64-Kb SPI device organized as 8Kx8 bits. This has a 64-byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through the Chip Select (CS) input. Also required bus signals are the clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input can be used to suspend any serial communication with the CAT25640 device. The device features software and hardware write protection, including partial as well as full array protection.

feature

Compatible with 20 MHz (5 V) SPI

1.8 V to 5.5 V supply voltage range

SPI mode (0,0) and (1,1)

64 byte page write buffer

Self-timed write cycle

Hardware and software protection

Block Write Protection - Protects 1/4, 1/2 or the entire EEPROM array

Low power CMOS technology

1,000,000 program/erase cycles

100 years data retention

Industrial and Extended Temperature Range

SOIC, TSSOP 8-pin and UDFN 8-pad packages

The device is lead-free, halogen-free/BFR, RoHS

Functional Symbol Diagram

PIN configuration diagram

Absolute Maximum Ratings

Operating temperature -45 to +130°C

Storage temperature -65 to +150°C

Voltage on any pin relative to ground (Note 1) -0.5 to +6.5 V.

Stresses beyond those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During conversion, the voltage on any pin may undershoot to not lower than -1.5 V or overshoot to not exceed VCC + 1.5 V for less than 20 ns duration.

reliability characteristics

Symbolic parameter minimum unit

1.NEND (Note 3) Endurance 1,000,000 program/erase cycles

TDR data retention for 100 years

2. Test these parameters initially and after design or process changes affecting the parameters according to appropriate AEC-Q100

and JEDEC test methods.

3. Page mode, VCC = 5 V, 25°C

Pin Description

SI: Serial data input pin accepts opcode, address and data. In SPI modes (0,0) and (1,1), incoming data is latched on the rising edge of the SCK clock input.

SO: The serial data output pin is used to transmit data to the device. In SPI modes (0,0) and (1,1), data is shifted out on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock provided by the host for synchronous communication between the host and the CAT25640.

CS: Chip select input pin is used to enable/disable CAT25640. When CS is high, the SO output is tri-stated (high)

impedance) and the device is in standby mode (unless an internal write operation is in progress). Each communication session between the host and the CAT25640 must start with a transition from high to low and end transition from low to high for the CS input.

WP: Write Protect input pin will allow all write operations to the device while high. Writing to the status register is disabled when the WP pin is low and the WPEN bit in the status register (see Status Register Description, later in this data sheet) is set to '1'.

HOLD: The HOLD input pin is used to suspend transmission between the host and the CAT25640 without retransmitting the entire sequence at a later time. To suspend, HOLD must be taken low and to resume it must be brought back high, with the SCK input low during both conversions. The HOLD input should also be tied to VCC directly or through a resistor when not in hold.

Function Description

The CAT25640 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8-bit instruction register. Instructions Table 9 lists the settings and associated opcodes. Reading the data stored in the CAT25640 is done by simply providing the READ command and the address. Writing to the CAT25640, as well as writing commands, addresses and data, also requires the device to be enabled for writing to first set certain bits in the state register, which will be explained later. After a high-to-low transition on the CS input pin, the CAT25640 will accept any of the six instructions. The opcodes listed in Table 9 will ignore all other possible opcode 8-bit combinations. The communication protocol is as shown in the following figure.