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2022-09-15 14:32:14
OPA2830 is dual, low power consumption, single power supply, broadband computing amplifier
Features
High Bandwidth: 230MHz (g u003d+1), 100 Might (G u003d+2)
Low power current: 7.8ma (7.8ma ( Vs u003d+5V)
Flexible supply range:
± 1.5V to ± 5.5V dual power supply
+3V to+11V single power supply [123 123 [123 ]input range includes single power ground ground
4.82VPP output switching+5V power supply
High conversion rate: 500V/μs
Low input voltage noise: 9.2NV/√Hz
Provide MSOP-8 software package
Application
#8226; Single power ADC input buffer
Single power video line drive
CCD imaging channel
low power ultrasound wave wavePLL Points
Portable consumer electronics
Low -power source filter
Explanation
OPA2830 is a dual, low power consumption, single power supply, broadband, voltage feedback amplifier, designed for single+3V or+5V power supply. It also supports running on ± 5V or+10V power supply. The input range is extended to the ground below the ground and within the 1.8 volt range of the positive power supply. Using a complementary public emission pole output, when driving 150 the output swing is within the 25 millivoltage and+V range of the ground. High -output -driven current (75mA) and low difference gain and phase errors have also made it an ideal choice for single -power consumer video products.
High -gain bandwidth (100MHz) and conversion rates ensure low distortion operations (500V/μs), making OPA2830 an ideal input buffer level of 3V and 5V CMOS modulus converters (ADC). Unlike the early low -power single power supply amplifiers, distortion performance increased with the signal amplitude decrease. Low 9.2NV/√Hz Input voltage noise supports wide dynamic range operation.
OPA2830 uses industry standard SO-8 packaging. OPA2830 also offers small MSOP-8 packaging. For fixed gains and line drives, please consider OPA2832.
Related Products
Single power supply,Differential, second -order, 5MHz, low -pass SALLEN key filter 
Order information
(1), the latest packaging and ordering information, see ""Appendix of Package Options"" at the end of this document.
Typical features: vs u003d ± 5V 
ta u003d+25 ° C, RF u003d 604 (as shown in Figure 17), RL u003d 500 unless there is another explanation. 
Unless otherwise explained, otherwise TA u003d+25 ° C, G u003d+2V/V, RF u003d 750 , RL u003d 150 #8486 ; To vs/2, enter VCM u003d 2.5V (see Figure 70).
TA u003d+25 ° C, RF u003d 604 , RL u003d 500 #8486; Differential (as shown in Figure 45), unless there is another explanation. 
ta u003d+25 ° C, g u003d+2v/v, RL u003d 150 #8486 ; To vs/3, unless there is another explanation (see Figure 71).
Typical features: vs u003d+3v
TA u003d+25 ° C, RF u003d 604 #8486;, RL u003d 500 Differential (as shown in Figure 64), unless there is another explanation. 
Application information
Broadband voltage feedback operation
OPA2830 is a unit gain stable, very high speed, very high -speed The voltage feedback computing amplifier is designed for single power operation (+3V to+10V). The input level supports the input voltage below the ground and within the 1.7V range of the positive power supply. The complementary agglomeration pole output level provides a ground and positive power supply within 25 millivolves. OPA2830 has been compensated and can run stably under various resistance loads. 
FIG. 70 shows AC coupling +2 gain configuration and typical characteristic curve for+5V specifications. Input impedance for testing purposesSet to 50 , the resistor is connected. The voltage fluctuations reported in the electrical characteristics are directly on the input and output pins. For the circuit in FIG. 70, the total effective load of high -frequency output is 150 | | 1500 . 1.5K #8486 at the non -conversion input terminal provides a co -mode bias voltage. Their parallel combination is equal to the DC resistance at the inverter input (RF), which reduces the DC output offset caused by the input bias current.
FIG. 71 shows the AC coupling +2 gain configuration for+3V specifications and typical characteristic curves. The voltage fluctuations in the electrical characteristics are directly collected at the input and output pins. For the circuit in FIG. 71, the total effective load of high -frequency output is 150 | | | 1500 The 1.13k and 2.26k the resistor provides a common mode bias voltage. Their parallel combination is equal to the DC resistance at the inverter input (RF), which reduces the DC output offset caused by the input bias current.
FIG. 72 shows DC coupling +2 gain dual -power circuit configuration as ± 5V electrical characteristics and typical characteristics. For the purpose of testing, the input impedance is used to set the input impedance to 50 , and the output impedance is set up to 150 The voltage fluctuation reported in the specification is directly measured at the input and output pin. Circuit diagram 72 The effective load is 150 | | 1.5K . Figure 72 includes two optional components. The additional resistor (348 ) is connected in series with non -swap input. Coupled with 25 DC power supply resistance back to the signal generator. And offset control part). In addition to the usual power supply container, a 0.01 μF capacitor also includes a 0.01 μF capacitor. In the actual PC plate layout, this optional electrical container usually increases the two harmonic distortion performance by 3 to 6 decibels. 
Single power ADC interface 
FIG Move up to adapt to the required output voltage range. Given the required signal gain (G), and the amount of VOUT (ΔVout) that needs to be moved up when VIN needs to move up in the center of its range. Suppose R4 is between 200 and 1.5k .
ensure that VIN and Vout remain within the specified input and output voltage range. 
The circuit in FIG. 73 is a good example of this application. When the+3V power supply is used, it is designed to obtain VIN between 0V and 0.5V and generates VOUT between 1V and 2V. This means g u003d 2.00, ΔVout u003d 1.50V #1504; 0.25V u003d 1.00V. Display these values u200bu200binto the above equation (R4 u003d 750 ) to get: ng u003d 2.33, R1 u003d 375 , R2 u003d 2.25K , R3 u003d 563 For the circuit in FIG. 73, the resistor is changed to the closest standard value. 
Low -power and low -cost video cable drives usually output buffer with a digital modular converter (DAC) output to the dual -end lines. These interfaces usually need DC blocking capacitors. For a simple solution, the interface usually uses a very large value to block the capacitor (220 μF) to limit the tilt or depression between the frames. Figure 76 shows a method of using much lower capacitance to create a very low Qualcomm polar position. The circuit provides a voltage gain at the output pin, and Qualcomm is located at 8Hz. Considering the 150 load, a simple blocking capacitor method requires 133 μF. Using this simple curved correction circuit in FIG. 76, the two capacitors with much lower value give the same low pass pole.
In FIG. 76, the sortee of the positive power supply will be moved slightly. At the cutting -edge part of the video signal, when the DAC output is zero current, this will generate about 200mV input DC offset, and it is displayed at 400mv DC offset at the output pin. This will keep the output in its linear working area. This will pass any power noise to the output, and the gain is about -20dB, so it is recommended to perform good power supply to the power pins. FIG. 75 shows the frequency response of the circuit in Figure 76. This picture shows the 8Hz low -frequency height magnetic pole and the height of about 100MHzEnd cut.
Non -mute amplifier reduced peaks
Figure 77 shows a non -conversion amplifier, which reduces the peak at low gain. The resistor RC compensates OPA2830 to obtain higher noise gain (NG), thereby reducing the peak of AC response without changing DC gains (usually 4dB when G u003d+1, no RC). VIN must be a low -impedance source, such as operational amplifier.
The unit gain buffer can be selected by selecting RT u003d RF u003d 20.0 # 8486; and RC u003d 40.2 (Do not use RG) to design. This makes the noise gain 2, so the response will be similar to the characteristic diagram of G u003d+2, with less peak values.
Single power supply active filter
OPA2830 runs on a single+3V or+5V power supply, which is very suitable for high -frequency active filter design. The key additional requirement is to establish a DC working point near the point of the power supply to obtain the highest dynamic range. Design examples of Tabat Waterwood 1MHz low -pass filter.
The input signal and the gain setting the resistor use 0.1 μF blocking capacitors for AC coupling (when the low -frequency pole of the component value is set to 32kHz, the actual response is actually given). This allows two 1.87k midpoint partial pressure formed by the resistor to appear on the input and output pin. In this case, the mid -frequency signal gain is set to +4 (12DB). The intended to input -oriented to input to the ground capacitor is designed as a higher value to control the input parasitic item. When the gain is +4, the OPA2830 on a single power supply will display a 30MHz size signal bandwidth. At the amplifier level, the filter resistance value has been slightly adjusted to consider this limited bandwidth. The test of the circuit shows that when the -3DB bandwidth of the amplifier is 30MHz, it has a very flat band (higher than 32kHz AC coupling angle), and the maximum resistance belt attenuation is 36DB. 
Differential low -pass active filter
Dual OPA2830 provides a simple way to achieve low -power differences with source filters. On a single power supply, a method of implementing a second -order low -pass filter is shown in Figure 79. The circuit provides a net difference in gain gain and precise 5MHz Bartworth response. The signal is coupled with the DC working point of the circuit set by the unit gain buffer BUF602 (provides Qualcomm pole at low frequency). This buffer provides very low output impedance for high frequency to maintain accurate filter characteristics. If this source is a DC coupling signal, it has been biased to OPA2830 to enter CMR's working rangeInside, these capacitors and mid -point bias can be removed. In order to get the required 5MHz deadline, the input resistance of the filter is actually 119 This is implemented in FIG. 79. As part of the DC bias network, the difference in the two 238 the parallel combination of the two 238 If you remove the BUF602, these resistors should be folded back to a single 119 input the resistor.
To achieve DC bias in this way, the differential signal will be attenuated by half. By setting the amplifier gain to 2V/V to obtain the characteristics of the NetUnity gain filter from input to output, this can be restored. The filter design shown here also slightly adjusted the resistance value from the ideal analysis to explain the 100MHz bandwidth of the amplifier level. The filter capacitor of non -switching to the input is displayed as two independent grounded capacitors. Of course, the two capacitors are folded into a capacitor at the two input terminals (50pf) to obtain the same differential filtering characteristics. The test shows that the two independent capacitors are connected to a low impedance point, which can attenuated circuit at the circuit at the circuit. The existence of co -mode feedback provides more stable operations in actual implementation. Figure 80 shows the frequency response of the filter in Figure 79.
Qual -pass filter
FIG. 81 shows another method of medium supply partial pressure. This method uses bypass removal instruments to replace the buffer used in Figure 79. The impedance is set up by the parallel combination of the resistance of the frequency portal network, but as the frequency increases, it looks more and more like a short -circuit caused by a capacitor. Generally speaking, the capacitance value needs to be more than two to three digital magnitude more than the filtering electrical values u200bu200bshown in order to make the circuit work normally.
FIG. 82 shows the frequency response of the circuit in Figure 81.
High -performance DAC cross -blocking large device
High -frequency video number modular converter (DAC) can sometimes benefit from low -distorted output amplifiers to maintain its SFDR Performance to the real world load. FIG. 83 shows the implementation of differential output drivers. The figure shows the signal output current connected to OPA2830, which is set to a cross-resistant level or I-V converter. If the DAC requires its output to be connected to a compliance voltage other than ground, the appropriate voltage level can be applied to the non -conversion input terminal of OPA2830. The DC gain of this circuit is equal to radio frequency. In high frequency, the DAC output capacitor (CD in Figure 83) will generate zero in the noise gain of OPA2830, which may cause the peak of the closed -loop frequency response. Add CF to the RF to compensate for the peak of noise gain. In order to achieve a flat cross -resistant frequency response, the pole point in each feedback network should be set to:
The dead frequency F -3DB is about: 
Design tool
Demonstrate fixed device [ 123]
Macro model and application support
The use of SPICE to simulate the circuit performance, which is usually a fast way to analyze OPA2830 and its circuit design. This is especially true for video and radio frequency amplifiers, because parasitic capacitors and inductors will play a main role in circuit performance. The spice model about OPA2830 can be obtained through the Ti webpage (website). The application department can also provide design assistance. These models predict typical small signal communication, transient jump, DC performance and noise under various working conditions. The model includes noise items in the electrical specifications of the data meter. These models do not try to distinguish the encapsulation type in its small signal communication performance.
Operation suggestion
Optimized resistance value
Since OPA2830 is a stable voltage feedback amplifier with a stable unit gain, feedback and gain setting resistors can use a wide range of resistance values u200bu200bin range resistance values Essence The main limitations of these values u200bu200bare set by dynamic range (noise and distortion) and parasitic capacitors. For non -ease units gain followers, the feeding connection should be directly short -circuited. 
A good rule of experience is to set the parallel combination of RF and RG (see Figure 72) to less than 400 . The combination impedance RF | | RG interacts with inverter input capacitors, adding a pole to the feedback network, so that the positive response is zero. Assuming the parasitic 2PF on the reverse node, keep RF | | RG LT; 400 it will keep the pole above 200MHz. As far as it is concerned, this constraint means that the feedback resistance RF can increase to several K under high gain. As long as the parasitic capacitance formed by RF's magnetic poles and parallel is not within the frequency range of interest, this is acceptable. In the reverse configuration, you must pay attention to the additional design considerations. RG becomes the input resistance, so it becomes a load impedance of the driver source. If the impedance match is required, the RG can be set to the required terminal value. However, at low reverse gains, the feedback resistance value generated will generate important loads for the output of the amplifier. For example, if the inverter gain is 2 and the input matching resistance is 50 (u003d rg), a feedback resistor of 100 this will help the output load connect with the external load. In this case, it is best to increase the RF and RG values u200bu200bat the same time, and then use the third ground resistance to input matching impedance (see Figure 84). The total input impedance becomes a parallel combination of RG and an additional parallel resistor.
Bandwidth and gain: No reversal operation
As the signal gain increases, the closed bandwidth of the voltage feedback Territories gradually decreases. Theoretically, this relationship is described as a width bandwidth (GBP) displayed in the specification. Ideally, in addition to GBP, in addition to the gain without reversing signal (also known as noise gain, or NG), a closed -loop bandwidth can be predicted. In fact, it was established when the phase hameness is close to 90 °, just like in a high -gain configuration. At low gain (increase feedback factor), most amplifiers will show more complicated responses and low phase margin. OPA2830 is compensated, and a minor peak response is given (see Figure 72) with the non -reversible gain (see Figure 72). This causes a typical gain of 105MHz to be +2 bandwidth, far exceeding 105MHz GBP except the prediction value of 2. Increasing gain will make the phase margin close to 90 °, and the bandwidth is closer to the predicted value (GBP/NG). When the gain is +10, the 10MHz bandwidth displayed in the electrical feature is consistent with the bandwidth of the typical GBP prediction of 105MHz.
The frequency response of the gain to +2 can be abnormally flat by increasing the noise gain to 3. Without affecting the +2 signal gain, one method is to add a 2.55k as shown in Figure 77. In the application of unit gain (voltage follower), similar technologies can be used to reduce peak values. For example, by using a 750 feedback resistor and a 750 resistor at the input terminal of the two computing amplifiers, the voltage follower response will be similar to the +2 response gain in FIG. 71. Further reducing the resistance value of the input terminal of the operation amplifier will further inhibit the frequency response caused by increasing noise gain. Compared with ± 5V, OPA2830 shows the minimum bandwidth decrease when working in a single power supply (+5V). This minimum reduction is because the total power supply voltage of the internal bias control circuit between the power pins maintains almost constant static currents.
Reverse amplifier operation
All familiar computing amplifiers application circuits can be provided to the designer with OPA2830. Figure 84 is a typical inverse configuration. The input/output impedance and signal gain in FIG. 70 retains the configuration in the inverter circuit. Reversal operation is one of the more common requirements, and it provides some performance advantages. It also allows input to bias to VS/2 without any net empty problem. The output voltage can move independently to the coupling capacitor within the output voltage range, or the bias adjustment resistance.
In the reverse configuration, you must pay attention to three key design considerations. First of all, the gain resistance (RG) becomes a signal channel input impedance. If you need to input impedance matching (when the signal is coupled when the signal is coupled by cable, twisted pad, long PC board wire or other transmission wire conductors, this is beneficial), you can set the RG to The required gain. This is the easiest way to get the best bandwidth and noise performance.
However, at low reverse gains, the feedback resistance value generated can provide an important load for the amplifier output. For the reverse gain of 2, set RG to 50 for input matching, no RM, but 100 feedback resistor. This structure has an interesting advantage, that is, for 50Ω source impedance, noise gain is equal to 2, which is the same as the non -conversion circuit considered above. The amplifier output will now see 100 feedback resistors that are connected to the external load. Generally, the feedback resistance should be limited to the range of 200 to 1.5k In this case, it is best to increase the RF and RG values u200bu200bat the same time, as shown in Figure 84, and then use the third resistor (RM) to achieve the input matching impedance ground. The total input impedance becomes a parallel combination of RG and RM.
The second main consideration mentioned in the previous paragraph is that signal source impedance becomes part of the noise gain equation, which affects the bandwidth. For the examples in FIG. 84, the RM value is combined with the external 50 source impedance (under high frequency) to produce an effective driving impedance of 50 | | | 57.6 u003d 26.8 This impedance is connected in series with RG to calculate noise gain. For Figure 84, the noise gain generated is 2.87, and if the RM can be eliminated as mentioned above, only 2. Therefore, the bandwidth (NG u003d+2.87) of the gain in FIG. 84 will be lower than the bandwidth of the +2 circuit in Figure 70 to the +2 circuit.
The third important consideration in the design of the inverter amplifier design is to set the bias current to offset the resistor (RT u003d 750 parallel combination) in the non -transient input terminal. If the resistance is set to the total DC resistance from the inverter node, the output DC error caused by the input bias current will be reduced to (input offset current) by RF. When the DC closed lock capacitor connects with RG, in Figure 84, the DC power supply impedance seen from the inverter mode is only RF u003d 750 . In order to reduce the additional high -frequency noise introduced by resistance and power feedback, RT is bypass the capacitor.
Output current and voltage
OPA2830 provides excellent output voltage capacity. For the+5V power supply, under the air load conditions of+25 ° C, the output voltage is usually less than 90mV compared to the Renyi Electric Source Rail. 
Drive capacitance load
For the operational amplifier, the most demanding and most common load conditions are the capacitor load. Generally, the capacitance load is an additional external capacitance that is recommended to improve the linearity of ADC. High -speed and high -open cyclic gains like OPA2830, when the capacitance load is directly applied to the output pins, its stability and closed -loop response peak value is very sensitive. When the main consideration is frequency response flat, pulse response and/or distortion, the simplest and most effective solution is to insert a series isolation resistance between the output and capacitance load between the amplifier and the capacitance load. Sexual load is separated from feedback ring.
The typical characteristic curve shows the recommended RS and the frequency response generated by the recommended RS and the capacitance load and the frequency generated under the load. Parasitic capacitance load greater than 2PF will begin to reduce the performance of OPA2830. The long PC board trajectory, unsatisfactory cables, and connection with multiple devices are easy to exceed this value. Always consider this impact carefully, and add a recommended series resistor (see the circuit board layout guide) as close as possible to the output pins.
The standard for setting the RS resistor is the maximum bandwidth and flat frequency response at the load. When the gain is +2, the frequency response at the output pins has slightly reached its peak without a capacitance load, and a relatively high RS value is required to flatten the response under flat load. Increasing noise gain will also reduce peak values u200bu200b(see Figure 77).
distortion performance
OPA2830 has good distortion performance under 150 Compared with other solutions, it provides excellent performance on lighter load and/or on single+3V power supply. Generally speaking, the second harmonic will dominate the distortion before the base wave signal reaches a very high frequency or power level, and the three harmonic components can be ignored. Then focus on the second harmonic to increase the load impedance directly to improve the distortion. please rememberThe total load includes the feedback network; in the non -reversing configuration (see Figure 72), this is the sum of RF+RG, and in the reverse configuration, you only need to connect the RF with the actual load. Running differential inhibit second harmonics, as shown in the typical characteristic curve of differentials.
Noise performance
High conversion rate, stable unit gain, voltage feedback computing amplifier usually achieve conversion rate at the cost of high input noise voltage. However, the 9.2NV/√Hz input voltage noise of OPA2830 is far lower than that of similar amplifiers. Entering the reference voltage noise and two input reference current noise items (2.8Pa/√Hz) are combined, which can provide low output noise under various working conditions. Figure 85 Display the noise analysis model of the operation amplifier, including all noise items. In this model, all noise items are considered noise voltage or current density items, and the unit is NV/√Hz or PA/.
The total output spots noise voltage can be calculated as a square root of all square output noise voltage contributors. Formula 1 shows the general form of the output noise voltage shown in FIG. 85: