The ADS7841 is a 4-channel, 12-bit sampling analog-to-digital converter (ADC) with a synchronous serial interface. The resolution is programmable to 8-bit or 12-bit with a typical power consumption of 2mW at 200kHz throughput rate and +5V supply. The reference voltage (VREF) can vary between 100mV and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode that reduces power consumption to below

15μW. The ADS7841 operates down to 2.7V. The low-power, high-speed and on-board multiplexer ADS7841 is suitable for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS7841 is available in a DIP-16 or SSOP-16 package and is specified over the -40°C to +125°C (1) temperature range.

feature

Single Supply: 2.7V to 5V

4-channel single-ended or 2-channel differential input

Up to 200kHz conversion rate

±1LSB MAX INL and DNL

no missing code

72dB SINAD

serial interface

DIP-16 or SSOP-16 package

Alternate source for the MAX1247

ADS7841ES: +125°C version

application

data collection

Test and Measurement

Industrial Process Control

personal digital assistant

battery powered system

PIN configuration, top view

PIN description

1 + VCC supply, 2.7V to 5V

2 CH0 analog input channel 0

3 CH1 analog input channel 1

4 CH2 analog input channel 2

5 CH3 analog input channel 3

6 COM Ground Reference for Analog Inputs. Sets the zero-code voltage in single-ended mode. Connect this pin to ground or reference.

7 SHDN shutdown. When low, the device enters a very low power shutdown mode.

8 VREF reference voltage input

9 + VCC supply, 2.7V to 5V

10 GND ground

11 MODE Conversion mode. When low, the device always performs 12-bit conversions. When high, the resolution is set by the MODE bits

CONTROL bytes.

12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. When CS is high, this output is high impedance.

13 BUSY busy output. When CS is high, this output is high impedance.

14 DIN Serial Data Input. If CS is low, data is latched on the rising edge of DCLK.

15 CS Chip Select Input. Controls conversion timing and enables serial input/output registers.

16 DCLK external clock inputs. This clock runs the SAR conversion process and synchronizes serial data I/O.

Theory of Operation

The ADS7841 is a classic successive approximation register (SAR) ADC. The architecture is based on capacitive redistribution, which essentially includes a sample-and-hold function. The converter is fabricated in a 0.6μs CMOS process. This device requires an external reference and an external reference clock. It operates from a single supply of 2.7V to 5.25V. This external reference voltage can be anywhere between 100mV and 100mV + VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the slew rate of the ADS7841. The analog inputs to the converter are differential inputs provided through a four-channel multiplexer. Inputs can be either providing the voltage on the COM pins (of which two of the four are typically used to differentiate or differential input channels (CH0 - CH3). The specific configuration is selectable via the digital interface.

Basic operation of the ADS7841

analog input

The following figure shows the block diagram of the input multiplexer ADS7841. The differential input of the converter is derived from one or two of the four inputs referenced to COM. This control bit is provided serially through the DIN pin,

When the converter enters holdover mode, the difference between the voltages +IN and -IN inputs (as shown in the figure below) is captured on the internal capacitor array. The voltage on this -IN input is limited to 1.25V between -0.2V and -0.2V, allowing the input to reject small signals common to the +IN and -IN inputs. The +IN input has a range of -0.2V to +VCC + 0.2V. The input current on the analog input depends on the slew rate of the device. During sampling, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor is fully charged, there is no further input current there. The analog source for a charge transfer rate converter is a function of the slew rate.

reference input

The external reference sets the analog input range. The ADS7841 operates from a reference range of 100mV to +VCC. Remember that the analog input is

The difference between the +IN input and the -IN input, see Figure 2 above. For example, in single-ended mode, with a 1.25V reference, and the COM pin grounded, selecting the input channel (CH0-CH3) will correctly digitize the signal range as 0V to 1.25V. If the COM pin is connected to 0.5V, the input range of the selected channel is 0.5V to 1.75V. There are several key terms about the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weighting of each digital output code is also reduced. This is often referred to as the LSB (least significant bit size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will appear to increase in terms of LSB size as the reference voltage decreases. For example, if a given offset The quantizer is 2LSB with a 2.5V reference, and then typically 10LSB with a 0.5V reference. In each case, the actual device offset is the same, 1.22mV. Likewise, the digitized output is noisy or uncertain The resistance will increase as the LSB size decreases. The reference voltage is 100mV and the LSB size is 24µV. This level is lower than the internal noise of the device. As a result, the digital output code will be unstable and vary around the average value of a

The number of LSBs. The distribution of output codes will be Gaussian noise and noise can be reduced by simple averaging or applying a digital filter to the continuous conversion result. When using lower reference voltages, care should be taken to provide a clean layout, including adequate bypassing, clean (low noise, low ripple) power supplies, low noise references, and low noise input signals. Because of the smaller size of the LSB, the converter is also more sensitive to nearby digital signals and EMI.

The voltage going into the VREF input is not part of the directly buffered drive capacitance digital-to-analog converter (CDAC) ADS7841. Typically, the input current is 3µA with a 2.5V reference voltage. This value will vary in microamps depending on the conversion result. This reference current reduces the rate and reference voltage directly with the two conversions. As the current reference is plotted on each bit decision, clocking the converter more quickly in a given conversion period does not reduce the overall current consumption of the reference current. Digital Interface The figure below shows the typical operation of the ADS7841 digital interface. This diagram assumes that the source's digital signal is a microcontroller or digital signal processor with a basic serial interface (note that the digital input is overvoltage tolerant up to 5.5V regardless of +VCC). Each communication between the processor and the converter consists of eight clock cycles. A complete conversion can be accomplished with three serial communications for a total of 24 clock cycles on the DCLK input.

The first eight clock cycles are used to provide control of the byte through the DIN pin. When the converter has enough information about the following conversions to set the input multiplexer appropriately, it goes into acquisition (sample) mode. After three clock cycles, the control byte is complete and the converter enters conversion mode. At this point, the input sample-and-hold enters the hold state mode. The next twelve clock cycles implement the actual analog-to-digital conversion. The thirteenth clock cycle is required for the last bit of the conversion result. There are three more clock cycles required to complete the last byte (DOUT will be low).