XC7K160T-2FF676I

Manufacturer number:

XC7K160T-2FF676I

Manufacturer: Xilinx

illustrate:

FPGA - Field Programmable Gate Array XC7K160T-2FF676I

Lifecycle: New Product: New from this manufacturer.

data sheet:

XC7K160T-2FF676I Datasheet

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Specification

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Manufacturer: Xilinx

Product Category:FPGA - Field Programmable Gate Array

Product: Kintex-7

Number of logic elements: 162240

Number of input/output terminals: 400 I/O

Operating supply voltage: 1.2 V to 3.3 V

Minimum operating temperature:- 40 C

Maximum operating temperature: + 100 C

Installation style: SMD/SMT

Package/Case: FCBGA-676

Data rate: 6.6 Gb/s

Series: XC7K160T

Trademark: Xilinx

Distributed RAM: 2188 kbit

Embedded Block RAM - EBR: 11700 kbit

Maximum operating frequency: 640 MHz

Humidity Sensitivity: Yes

Number of Transceivers: 8 Transceiver

Product Type:FPGA - Field Programmable Gate Array

Factory Packing Quantity: 1

Subcategory: Programmable Logic ICs

Brand Name: Kintex

Kintex®-7 FPGA

Xilinx Kintex™-7 FPGAs provide optimal price/performance and low power consumption for fast-growing applications and wireless communications. Kintex-7 FPGAs offer superior performance and connectivity at prices previously limited to higher-volume applications.

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Mixed-Mode Clock Manager and_Phase-Locked Loop

The MMCM and_PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies

and_as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which

speeds up and_slows down depending on the input voltage it receives from the phase frequency detector (PFD).

There are three sets of programmable frequency dividers: D, M, and_O. The pre-divider D (programmable by configuration

and_afterwards via DRP) reduces the input frequency and_feeds one input of the traditional PLL phase/frequency

comparator. The feedback divider M (programmable by configuration and_afterwards via DRP) acts as a multiplier because

it divides the VCO output frequency before feeding the other input of the phase comparator. D and_M must be chosen

appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases

(0°, 45°, 90°, 135°, 180°, 225°, 270°, and_315°). Each can be selected to drive one of the output dividers (six for the PLL,

O0 to O5, and_seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128.

The MMCM and_PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth

mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but

not the best jitter attenuation. Optimized mode allows the tools to find the best setting.

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