The CC1150 is a true single-chip UHF transmitter designed for ultra-low power wireless applications. This circuit is primarily intended for use in the ISM (Industrial, Scientific and Medical) and SRD (Short Range Devices) 315- , 433- , 868- and 915-MHz frequency bands, but can be easily programmed to operate in other frequency ranges from 300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz bands. The RF transmitter integrates a highly configurable baseband modulator. The modulator supports various modulation formats with configurable data rates up to 500 kBaud. The CC1150 device provides extensive hardware support for packet processing, data buffering and burst transfers. The main working parameters of CC1150 and the 64-byte transmit FIFO can be controlled through the SPI interface. In a typical system, the CC1150 device will use a microcontroller and a few additional passive components.

Functional block diagram

The CC1150 transmitter is based on direct synthesis of RF frequencies. The frequency synthesizer includes a fully on-chip LC VCO. The crystal will be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the frequency of the reference synthesizer, as well as the clock for the digital section. A 4-wire SPI serial interface is used for configuration and data buffer access. Digital baseband includes support for channel configuration, packet processing and data buffering.

Configuration overview

The CC1150 can be configured for optimum performance in many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

Power-down and power-up modes

Crystal Oscillator Power-Up and Power-Down

transfer mode

RF channel selection

data rate

modulation format

RF output power

Data buffering using 64-byte transmit FIFO

Packet Radio Hardware Support

Forward Error Correction with Interleaving

Data whitening

The CC1150 can be configured using SmartRF Studio [11] software. SmartRF Studio software is highly recommended for obtaining optimal register settings, as well as evaluating performance and functionality. A screenshot of the CC1150's SmartRF Studio user interface is shown below.

4-wire serial configuration and data interface

The CC1150 configures the CC1150 as a slave via a simple 4-wire SPI compatible interface (SI, SO, SCLK and CSn). This interface is also used to read and write buffered data. All address and data transfers on the SPI interface are the most significant bit first. All transactions on the SPI interface begin with a header byte containing read/write bits, burst access bits, and a 6-bit address. During address and data transfers, the CSn pin (chip select, active low) must be held low. If CSn goes during the visit, the transfer will be cancelled. address and time of data transfer.

Chip Status Byte

When a header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1150 to the SO pin. Status bytes contain key status signals and are useful to the MCU. This first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first rising edge of SCLK. The CHIP_RDYn signal indicates that the crystal oscillator is running and the regulated digital supply voltage is stable.

Bits 6, 5 and 4 include the STATE value. This value reflects the state of the chip. The XOSC and power digital core are in IDLE state, but all other modules are powered down. frequency and channel configuration should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

Real-world data often contains long sequences of 0s and 1s. Performance can then be improved by whitening the data before sending, and dewhitening in the receiver. In combination with CC1150, CC1101 on the receiver side, this can be done automatically by setting PKTCTRL0WHITE_DATA = 1. All then, the data except the preamble and sync word are XORed with 9-bit pseudo-random (PN9) The PN9 sequence before transmission is initialized to all 1s. On the receiver side, the data is XORed with the same pseudo-random sequence. In this way, the whitening is reversed and the original data appears in the receiver. Setting PKTCTRL0.WHITE_DATA = 1 is recommended for all uses except wireless compatibility

with other systems is required.

The preamble pattern is an alternating sequence of 1s and 0s. The number of preamble bytes written using the MDMCFG1.NUM_PREAMBLE value. When TX is enabled, the modulator will start sending the preamble. If data is available when the programmed number of preamble bytes is available, the modulator will send the sync word followed by the data from the TX FIFO. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word followed by the data byte. The sync word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of incoming packets. The single-byte sync word SYNC1 value can be emulated by setting to preamble mode. A 32-bit sync word can also be emulated by using MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice.

C1150 supports fixed packet length protocol and variable packet length protocol. Variable or fixed packet length modes are available for packets up to 255 bytes. For longer packets, infinite packet length mode must be used. Fixed packet length mode is selected by PKTCTRL0.LENGTH_CONFIG = 0. The required packet length is set by the PKTLEN register. In variable packet length mode PKTCTRL0.LENGTH_CONFIG = 1, the packet length is configured by the first byte after the sync word. Packet length is defined as payload data, excluding length bytes and optional automatic CRC. When using PKTCTRL0.LENGTH_CONFIG = 2, the packet length is set to infinite, and the transfer will continue until manually turned off infinite mode can be turned off when transmitting packets. As described in Section 5.8.2.1, this can be used to support packet formats with different length configurations than the CC1150 natively supports. It should be ensured that the TX mode is not turned off to transmit the first half of any byte during this time. See CC1150 Errata Note [8] for more details. The minimum supported packet length (excluding optional length bytes and CRC) is one byte of payload data. 5.8.2.1 Arbitrary Length Field Configuration Packet Automation Control Register PKTCTRL0 can be reprogrammed during TX. This opens up the possibility to transmit packets longer than 256 bytes and still use packet processing hardware support. Infinite mode (PKTCTRL0.LENGTH_CONFIG = 2) must be active at the start of the packet. The PKTLEN register is set to mod(length, 256). When the packet has less than 256 bytes remaining, the MCU disables unlimited packet length and activates fixed-length packets. When the internal byte counter reaches the PKTLEN value, the transmission ends (the radio enters the state determined by TXOFF_MODE). Automatic CRC appending can be used (by setting PKTCTRL0.CRC_EN = 1).

For example, when a 600 -byte packet is to be transmitted, the MCU should do the following (see also the figure below):

Set PKTCTRL0.LENGTH_CONFIG = 2.

Preprogram the PKTLEN register to mod(600,256) = 88.

Send at least 345 bytes, e.g. by filling the 64-byte TX FIFO six times (384-byte send).

Packet processing in transmit mode must write the payload to be transmitted into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The value of the length byte is equal to the payload packet (including the optional address byte). If fixed packet length is enabled, the first byte is written. If this feature is enabled in the device, the TX FIFO is interpreted as the destination address to receive packets.

The modulator will first send the programmed number of preamble bytes. If the data is available in the FIFO in TX, the modulator will send a two-byte (optionally 4-byte) sync word followed by the payload FIFO in TX. If CRC is enabled, the checksum result is calculated on all data extracted from the TX FIFO and TX is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before completing the packet transmission, the radio will enter the TXFIFO_UNDERFLOW state. The only way to get out of this state is by issuing an SFTX strobe. Writing to the TX FIFO after underflow does not restart TX mode. If whitening is enabled, the length byte, payload data and both CRC bytes will be whitened. This is done before the optional FEC/interleaver stage. Enable whitening by setting PKTCTRL0.WHITE_DATA = 1. If FEC/Interleaving is enabled, the length byte, payload data and two CRC bytes will be scrambled by the interleaver, along with the FEC encoded before modulation. Enable FEC by setting

MDMCFG1.FEC_EN = 1. 5.8.4 Packet Handling in Firmware When implementing a packet-oriented radio protocol in firmware, the MCU needs to know when a send packet has been propagated. Also, for packets longer than 64 bytes, the TX FIFO needs to be refilled

And in TX. This means that the MCU needs to know the number of bytes that can be written to the TX FIFO. There are two possible solutions to get the necessary status information: one. Interrupt Driven Solution - The GDO pin can be used for TX to generate an interrupt when a sync word is sent or when a complete packet is transmitted by setting IOCFGx.GDOx_CFG = 0x06.