The FIN12AC is a 12-bit serializer capable of operating for a parallel frequency range between 5MHz and 56MHz. The control of S1 and S2 selected in this frequency range is excellent. Bidirectional data flow is controlled through the use of a directional (DIRI) control pin. The device can be configured to operate on the DIRI pin in unidirectional mode only by hardwiring. An internal PLL generates the required bit clock frequency for transmission over the serial link. The option exists for single or dual PLL operation depending on the system TEM operating parameters. The device has been designed for low-power operation and utilizes Fairchild's pro-proprietary low-power CTL interface. The device also supports an ultra-low-power power-down mode for a port to save power for battery-powered applications.

Functional block diagram

control logic circuit

FIN12AC must be used as a 12-bit capable Serial-izer or 12-bit deserializer. Terminals S1 and S2 must be grouped to accommodate serialization of the clock reference input frequency range. The table below shows the terminals based on the programming control terminals S1 and S2 for these options. The DIRI terminal controls whether the device is a serializer or deserializer. If DIRI is set low, the device is configured as a deserializer. When the DIRI terminal is set high, the device is configured as a serializer. Changing the state of the DIRI signal will reverse the direction of the I/O signal and generate the opposite state of the DIRO signal. For unidirec-tional operation the DIRI terminal shall be hardwired high or low and the DIRO terminal shall be left floating. For bidirectional operation the DIRI master will be driven by the system and the DIRO signal of the master will be used to drive the DIRI slave.

Power-down mode

Mode 0 is used to power down and reset the device. When the two modulo signals are driven to a low state the PLL and reference will be disabled, the differ-infinity interval input buffers will be turned off, the differential output buffers will be placed into a high impedance state, and the LVCMOS outputs sell option will be placed into a high impedance state, and the LVC-MOS input will be driven to an internal effective level. Also, all internal circuits will be reset. The loss of CKREF status is also enabled to ensure that the PLL will only power up if there is a valid CKREF signal. In a typical application of the device the mode signal will not change outside the desired frequency range between and power down mode. This allows system-level power-saving features to be implemented through a single line for a serdes pair. The select signals for S1 and S2 have been driven to 'logic 0' in operating mode and should be connected to GND. The S1 and S2 signals have to be driven as "logic 1" in the operating mode should CON be connected to the system level power down signal.

serial operation mode

Serial configuration is in the description section below. The basic serialization circuit works basically in these modes, but the actual data and clock streams will be different depending on if CKREF is the same as the strobe signal or not. When it is called CKREF strobe, it means that the CKREF and STROBE signals have the same frequency of action, but may or may not coincide. When it is pointed out that CKREF is not equal to STROBE then each signal is different and CKREF must be at a frequency high enough to avoid any case of running lost data. CKREF is by no means a lower frequency Quincy strobe.

Connection Diagram