The AD9762AR is a 12-bit resolution member of the TxDAC family of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family consists of pin-compatible 8-bit, 10-bit, 12-bit and 14-bit DACs optimized for the transmit signal path of communication systems. All devices share the same interface options, small form factor packages and pinouts, providing up or down component selection path costs based on performance, resolution and components.

The AD9762 has excellent ac and dc performance while supporting update rates up to 125 MSPS. The flexible single-supply operating voltage range of 2.7 V to 5.5 V and low power consumption of the AD9762 are ideal for portable and low-power applications. Its power consumption can be further reduced to just 45 mW without significant performance degradation by reducing the full-scale current output. Also power-down mode reduces standby power consumption to approximately 25 mW.

The AD9762 is fabricated using an advanced CMOS process. The segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. An edge-triggered input latch and a 1.2 V temperature compensated bandgap reference are integrated to provide a complete monolithic DAC solution. Flexible power options support +3 V and +5 V. CMOS logic families.

feature

Member of the pin-compatible TxDAC product family

125 MSPS update rate

12-bit resolution

Excellent spurious free dynamic range performance

SFDR to Nyquist @ 5 MHz output: 70 dBc

Differential Current Output: 2 mA to 20 mA

Power consumption: 175 mW @ 5 V to 45 mW @ 3 V.

Power-Down Mode: 25 mW at 5 V on-chip 1.20 V reference, single +5 V or +3 V supply operation

Package: 28-pin SOIC and TSSOP edge-triggered latches

application

Communication transmission channel:

Base station (single/multi-channel application)

ADSL/HFC modem

Direct Digital Synthesis (DDS)

meter

Functional block diagram

Differential current outputs are available to support single-ended or differential applications. Matched current outputs between the two ensure enhanced dynamic performance in differential output configurations. The current output may be connected directly to the output resistor, providing two complementary single-ended voltage outputs or fed directly into a transformer. The output voltage is compatible with a range of 1.25 V. The on-chip reference and control amplifiers are configured for maximum accuracy and flexibility. The AD9762 can be driven through the on-chip reference or through a variety of external reference voltages. The wide (>10:1) adjustment range provided by the internal control amplifier allows the AD9762 full-scale current to be adjusted from 2 mA to 20 mA while maintaining excellent dynamic performance. As a result, the AD9762 can operate at reduced power levels or be adjusted to provide additional gain ranging capabilities within 20 dB.

The AD9762 is available in 28-lead SOIC and TSSOP packages. It is suitable for industrial temperature range.

Product Highlights

1. The AD9762 is a member of the TxDAC product family providing an up or down component selection path based on resolution (8 to 14 bits), performance and cost.

2. Manufactured in a CMOS process, the AD9762 uses a proprietary switching technology that improves dynamic performance beyond previous high-performance power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches are easily connected to +3 V and +5 V CMOS logic families. The AD9762 can support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 2.7 V to 5.5 V and a wide full-scale current regulation range of 2 mA to 20 mA allow the AD9762 to operate with reduced power consumption.

5. The current output of the AD9762 can be easily configured into a variety of single-ended or differential circuit topologies.

PIN configuration diagram

Definition of Specifications: Linearity Error (also known as Integral Nonlinearity or INL) Linearity error is defined as the actual analog output at maximum deviation from the ideal output, determined by a straight line from zero to full scale.

Differential Nonlinearity (or DNL) DNL is a measure of change in an analog value, normalized to full scale, associated with a 1 LSB change in a digital input

code.

Monotonicity: A D/A converter is monotonic if the output increases or it remains constant as the digital input increases.

Offset Error: The deviation of the output current from the ideal value of zero is called offset error. For IOUTA, the output input is all 0 when 0 mA is expected. For IOUTB, all expected 0 mA output inputs are set to 1 second.

Gain Error: Difference between actual and ideal output range. This actual span is determined by the output when all inputs are set when all inputs are set to 0, minus 1s minus the output.

Output Compliance Range: The allowable voltage range at the output of the current output DAC. Operation beyond the maximum compliance limits may result in output stage saturation or breakdown resulting in nonlinear performance.

Temperature Drift: Temperature drift is specified as the maximum changing ambient (+25°C) value to the value of TMIN or TMAX. For offset and gain drift, drift is reported in ppm of full scale range per degree C (FSR). For reference drift, drift is reported in ppm per degree Celsius.

Power Rejection: The maximum change in full-scale output as the consumable varies from nominal to minimum and maximum specified voltages.

Settling Time: The time it takes for an output to arrive and remain within a specified error band with respect to its final value, from which the output transition is measured to begin.

Glitch Impulses: Asymmetric switching times in DACs can create undesired output transients, quantified by glitch impulses. It is the net area of the glitch specified as pV-s.

Spurious Free Dynamic Range: The difference (in dB) between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion: THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. it is

Expressed as a percentage or decibels (dB).

Multitone Power Ratio: The spurious-free dynamic range of an output containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitudes of the carrier tones to remove peak spurs in the tonal region.

Basic AC Characterization Test Setup

The following figure shows a simplified block diagram of the AD9762. The AD9762 consists of a large array of PMOS current sources capable of delivering up to 20 mA total current. The array is divided into 31 equal currents consisting of 5 Most Significant Bits (MSBs). The next 4 or middle bits consist of 15 equal current sources with a value of 1/16MSB current sources. The remaining LSBs are part of a binary-weighted mid-bit current source. Replacing the R-2R trapezoid with a current source between implementations and low bits enhances the dynamics of its polyphonic or low-amplitude signals, helping to maintain the high-level output impedance of the DAC (ie, >100kΩ). All of these current sources are switched to one or the other of the two output nodes (i.e. IOUTA or IOUTB) via a PMOS differential current switch. These switches are based on a new architecture that significantly improves distortion performance. This new switch architecture reduces various timing errors and provides differential current switches that match complementary drive signals to the input.

The analog and digital sections of the AD9762 are separate and can operate on the power supply inputs (ie AVDD and DVDD) independent of the 2.7 volt to 5.5 volt range. The digital part, capable of running clock rates up to 125 MSPS, consists of edge-triggered latches and segment decoding to form logic circuits. The analog section includes a PMOS current source, associated differential switches, a 1.20 V bandgap voltage reference, and a reference control amplifier.

The full-scale output current is regulated by the reference voltage to control the amplifier, and can be programmed by an external resistor, RSET, from 2 mA to 20 mA. The external resistor combination uses the reference control amplifier and the voltage reference VREFIO to set the mirrored reference current IREF by appropriate scaling to divide the current source factor. The full-scale current, IOUTFS, is thirty-two times this value. The IREFDAC transfer function The AD9762 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a current output near full scale, IOUTFS, IOUTB is a complementary output when all bits are high (i.e. DAC CODE = 4095 ) and does not provide current. The current output that appears on IOUTA and IOUTB is a function of both input code and IOUTFS can be expressed as: IOUTA = (DAC code / 4096) × IOUTFS(1) IOUTB = (4095 - DAC code) / 4096 × IOUTFS(2) where DAC CODE = 0 to 4095 (ie, decimal representation).

As mentioned earlier, IOUTFS is a function of the reference current IREF, nominally set by the reference voltage REFIO and the external resistor RSET. It can be expressed as: IOUTFS = 32 × IREF(3) where IREF = VREFIO/RSET(4) Both current outputs will normally drive resistive loads directly or through a transformer. If DC coupling is required, IOUTA and IOUTB should be connected directly to matched resistive loads, RLOAD, which are connected to analog common ACOM. Note that RLOAD can represent the equivalent load resistance IOUTA or IOUTB just like a double terminated 50Ω or 75Ω cable. A single-ended voltage output appears on the IOUTA and IOUTB nodes simply:

VOUTA = IOUTA×RLOAD(5) VOUTB = IOUTB×RLOAD(6) Note that the full-scale values of VOUTA and VOUTB should not exceed the specified output compliance range to maintain the specified distortion and linearity performance. The differential voltage VDIFF appears at IOUTA and

IOUTB is: VDIFF = (IOUTA - IOUTB) × RLOAD(7) replace the values of IOUTA, IOUTB and IREF; VDIFF can be expressed as:

VDIFF = {(2 DAC CODE - 4095) / 4096} × (32 RLOAD / RSET) × VREFIO(8) The last two equations highlight some advantages of operating the AD9762 differentially. The first is that differential operation will help eliminate associated common-mode error sources

IOUTA and IOUTB, such as noise, distortion and DC offset. Second, the differential code depends on the current and the subsequent current voltage VDIFF is twice the single-ended voltage value of the output (ie VOUTA or VOUTB), thereby providing twice the signal to power the load. Note that the gain drift temperature performance of the single-ended (VOUTA and VOUTB) or the differential output of the AD9762 (VDIFF) can be enhanced by selecting a temperature tracking resistor

RLOAD and RSET are shown in Equation 8 due to their proportional relationship.

The AD9762's built-in 1.20 V bandgap reference can be easily disabled and overridden by external references. REFIO can be an input or an output, depending on whether an internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 40, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be externally compensated using REFIO's 0.1µF or higher ceramic chip capacitor. Additionally, the REFIO should be used with an external buffer amplifier whose input bias current is less than 100 nA (if any) requiring additional load.

The internal reference to AVDD can be disabled by connecting REFLO to AVDD. In this case, an external reference can then be applied to REFIO as shown in the figure below. An external reference can provide a fixed reference voltage for improved accuracy drift performance or a variable reference voltage for gain control. Note that the 0.1µF compensation capacitor is not required because the internal reference is disabled, and the high impedance of the input REFIO (i.e. 1MΩ) minimizes any loading of the external reference.

The control amplifier allows a wide (10:1) adjustment range by setting IREF, IOUTFS at 62.5 μA and 625 μA in the 2 mA to 20 mA range. The wide adjustment range of IOUTFS provides several application advantages. The first benefit concerns the power consumption directly for the AD9762, which is proportional to IOUTFS (see the Power Dissipation section). The second benefit is related to the 20 dB adjustment, which is useful for system gain control. The small signal bandwidth of the reference control amplifier is about 1.4 MHz and can be connected to reduce the external capacitance between COMP1 and AVDD. The output of the control amplifier COMP1 is internally compensated by a 50 pF capacitor, limiting the small-signal bandwidth of the control amplifier and reducing its output impedance. Any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise impact of the reference amplifier. The figure below shows the relationship between external capacitors and -3 dB bandwidth for small signals

reference amplifier. Since the -3 dB bandwidth corresponds to the dominant pole, the time constant, the time response of the stable control amplifier to the step reference input can be approximated. The best distortion performance of any reconstruction is obtained by installing a 0.1µF external capacitor waveform. Therefore, if IREF is fixed for the application, a 0.1µF ceramic chip capacitor is recommended. Additionally, since the control amplifier is optimized for low power operation, enabling application multiplication requiring large signal swing should consider using an external control amplifier to enhance the application's overall large signal multiplication bandwidth and/or distortion performance. There are two ways to change the fixed value of IREF, RSET.

The first method works for single-supply systems where internal references are disabled, and the voltage of the common-mode REFIO varies within the compliance range of 1.25 V. REFIO can be driven by a single-supply amplifier to the DAC, thus allowing IREF to vary for a fixed RSET. Since the input impedance of the REFIO is about 1MΩ, a simple, low-voltage R-2R ladder DAC configured in a voltage-mode topology can be used to control the gain. The circuit is shown in the figure below using the AD7524 and an external 1.2 V reference, the AD1580, in the above figure.

The second method can be used in dual-supply systems where the common-mode voltage of REFIO is fixed and IREF is changed by an external voltage, VGC, applied to RSET through an amplifier. An example of this method is shown in Figure 44. The internal reference is used to set the voltage of the common mode voltage controlled amplifier to 1.20 V. The external voltage VGC is referenced to ACOM and should not exceed 1.2 V. The result of this value for RSET is that IREFMAX and IREFMIN do not exceed 62.5µA and 625µA. The relevant equations in the figure below can be used to determine the value of RSET.

In some applications, the user may choose to use an externally controlled amplifier to enhance multiplying bandwidth, distortion performance and/or settlement time. An external amplifier capable of driving a 50 pF load (such as the AD817) is suitable for this purpose. It configures a weaker internal reference amplifier in parallel with it, as shown in the figure below. In this case, the external amplifier is just overdriving the weaker reference control amplifier. Also, since the internal control amplifier has a limited current output, it will not be damaged if overloaded.

Analog output

The AD9762 produces two complementary current outputs, IOUTA and IOUTB, that can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, through the load resistor RLOAD, as described in the DAC transfer function section represented by Equations 5 to 8. The voltage VDIFF present between differential VOUTA and VOUTB can also be converted to a single-ended voltage through a transformer or differential amplifier configuration. AC performance The AD9762 is optimal, specified using a differential transformer-coupled output, where the voltage swing of IOUTA and IOUTA, IOUTB, is limited to ±0.5 V. If a single-ended unipolar output is ideal, IOUTA should be selected.

The distortion and noise performance of the AD9762 can be enhanced when the AD9762 is configured for differential operation. Common-mode error sources for IOUTA and IOUTB can be significantly reduced by common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The improvement in distortion performance becomes more important as the frequency content of the reconstructed waveform increases. This is due to the first cancellation of the order

Various dynamic common-mode distortion mechanisms, digital punch-through and noise. Performing differential-to-single-ended conversion via a transformer also provides the ability to deliver twice reconstructed signal power to the load (ie, assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when differentially processed. A properly selected transformer will allow the AD9762 to provide the required power and voltage levels for different loads. See the Applying the AD9762 section Output Configuration for various examples. The output impedances of IOUTA and IOUTB are combined by the equivalent parallel connection of the PMOS switches associated with the current source, typically 100kΩ 5 pF in parallel. It also depends slightly on the output voltage

(ie, VOUTA and VOUTB) due to the nature of PMOS devices. Therefore, keeping IOUTA and/or IOUTB at virtual ground through an IV op-amp configuration will yield the best DC linearity. Note that the I??NL/DNL specification for the AD9762 is measured by maintaining a virtual ground for IOUTA, the op amp.