The CDCVF2510 is a high performance, low skew, low jitter, phase locked loop (PLL) clock driver. It uses a phase locked loop (PLL) to precisely align the feedback (FBOUT) output to the clock (CLK) input signal in frequency and phase. It is specifically designed for synchronous DRAM. The CDCVF2510 operates on 3.3V VCC. It also offers integrated series damping resistors, making it ideal for driving point-to-point loads. A set of 10 outputs provides 10 low-skew, low-jitter copies of CLK. The output signal duty cycle is adjusted to 50%, independent of the duty cycle of CLK. The output is enabled or disabled via the control (G) input. When the G input is high, the output switches in phase and frequency with CLK; when the G input is low, the output is in a disabled logic low state. Unlike many products that include a PLL, the CDCVF2510 does not require an external RC network. The loop filter PLL is packaged on-chip, minimizing component count, board space, and cost. Because it is based on a PLL circuit, the CDCVF2510 requires a settling time to achieve phase lock feedback to the reference signal. This settling time is required after power-up and application of a fixed frequency, fixed phase signal of CLK, or any change in the PLL reference or feedback signal. By tying AVCC to ground, the PLL can be bypassed for test purposes. The CDCVF2510 features an operating temperature range of 0°C to 85°C.

feature

Spread Spectrum Clock Compatible

Operating frequency 50 MHz to 175 MHz

66 MHz to 66 MHz static phase error distribution 166 MHz is ±125 ps

66 MHz to 166 MHz jitter (cyc-cyc) is |70|PS

Advanced deep submicron process results in more than 40% reduction in power consumption corresponding to contemporary PC133 devices

Available in plastic 24-pin TSSOP package

Phase-locked loop clock distribution for synchronous DRAM applications

Assign a clock input to a Bank10 item output

External feedback (FBIN) terminal for synchronizing the output to the clock input

25Ω On-Chip Series Damping Resistors

No external RC network required

The operating voltage is 3.3 V.

PW PACKAGE

(top view)

Terminal functions:

CLK provides the clock signal distributed by the CDCVF2510 clock driver. CLK is used to provide a reference signal to the integrated PLL that generates the clock output signal.

CLK 24 I CLK must have a fixed frequency and a fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, the PLL needs settling time to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must hardwire FBIN 13 I FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output library enabled. G is the output enable for output 1Y (0:9). When G is low, output 1Y (0:9) G 11 I disable the logic low state. When G is high, all outputs 1Y (0:9) are enabled and switched to the same frequency as CLK. feedback output. FBOUT is dedicated to external feedback. it switches at the same frequency as

FBOUT 12 O CLK. When connected externally to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25Ω series damping resistor.

3,4,5,8,9, clock output. These outputs provide low-skew copies of CLK. Output bank 1Y (0:9) passes

1Y (0:9) 15, 16, 17, 20, G input. These outputs can be disabled to a logic low state by deasserting the G control input.

21Each output has an integrated 25Ω series damping resistor. Analog power. AVCC provides the power reference for analog circuits. In addition, AVCC, AVCC 23 Power can be used to bypass the PLL for testing. When AVCC is grounded, the PLL is bypassed and CLK is buffered directly to the device output. AGND 1 Ground analog ground. AGND provides the ground reference for analog circuits.

Absolute Maximum Ratings:

(2) Power supply voltage range AVCC

(3) Input voltage range -0.5 V to 4.6 V.VO

(4) Voltage range for any output from high or low state -0.5 V to VCC + 0.5 V I IK (VI < 0) Input clamp current - 50 mAIOK (VO < 0 or VO > VCC) Output clamp current ±50 mAIO (VO = 0 to VCC) continuous output current ±50 mA VCC or GND each ±100 mA continuous current TA = 55°C (in still air)

(5) Maximum power consumption 0.7 WTstg Storage temperature range from -65°C to 150°C

(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device under these or any other conditions beyond those indicated in "Recommended Operation" is not implied. Prolonged exposure to absolute maximum rating conditions may affect device reliability .

(2) AVCC must not exceed VCC + 0.7 V.

(3) Input and output negative voltage ratings may be exceeded if input and output clamp current ratings are observed.

(4) The value is limited to a maximum of 4.6 V.

(5) Maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Sheet.

Parameter measurement information

A: CL includes probe and fixture capacitance.

B: All input pulses are powered by a generator with the following characteristics: PRR≤133MHz, ZO=50Ωtr≤1.2nstf≤1.2ns.

C: Outputs are measured one at a time, one conversion per measurement.

Load circuit and voltage waveform