Features ■ Two full-capacity 20 MHz DMA channels, each with 32-bit addressing and 16-bit data transfer.
■DMA mode includes single buffer, pipeline, array chain and linked array chain.
■The ring buffer function supports a circular queue of buffers in memory.
■Linked frame status transfer function Writes the status information of the received frame and reads the control information of the transmitted frame to the array or linked list of the DMA channel to significantly simplify the processing of frame status and control information.
In burst mode, the DMA bus occupancy can be adjusted programmable, and the bus occupancy time is limited.
■0 to 20 Mbit/s, full-duplex channel with two baud rate generators and a digital phase-locked loop for clock recovery.
32-byte data FIFOS for receiver and transmitter
■Up to 12.5 Mbytes/sec (16-bit) data bus bandwidth ■Multi-protocol operation under program control, receiver and transmitter have independent mode selection.
Asynchronous mode, 1 to 8 bits/character, 1/16 to 2 stop bits/character, in 1/16-bit increments; 16x, 32x, or 64x oversampling; interrupt detection and generation; odd, even, marks, spaces or no parity and framing error detection. Supports 9-bit and mil-std1553b protocols.
■ HDLC/SDLC mode with 8-bit address comparison; extended address field option; 16-bit or 32-bit CRC; programmable idle line condition; optional pre-transfer and loop modes. Optional number of flags between back-to-back frames.
Byte-oriented sync mode, 1 to 8 bits/character; programmable sync and idle line conditions; optional receive sync stripping; optional preamble transmission; 16-bit or 32-bit CRC; Transmitto Receive Slaving (for X. twenty one).
External character synchronization mode for reception Transparent double synchronization mode with EBCDIC or ASCII character code; automatic CRC processing; programmable idle line condition; optional pre-transmission; automatic identification of DLE, SYN, SOH, ITX, ETX, ETB, EOT , ENQ and ITB.
■Flexible bus interface, can be directly connected to most microprocessors; user programmable 8 or 16 bits wide. Directly support 680X0 series or 8X86 series bus interface.
■ Receive and transmit time slot allocation procedures for ISDN, T1 and E1 (CEP) applications.
8-bit general purpose port with transition detection Low power CMOS
68-pin PLCC assembly ■ Provides electronic programmer's manual supporting tools and software drivers.

General Notes (continued)
There are other reasons to use the Z16C32 IUSC than just reducing chip count and board space economy. The intercommunication of DMA and serial channels also provides application benefits. For example, events (such as the reception of the end of an HDLC frame) are transferred from within the serial controller to the DMA so that each frame can be written to a separate memory buffer. Buffer linking capability, ring buffer support, automatic frame status/control blocks, and buffer termination at end of frame combine to significantly reduce CPU overhead
The IUSC is software configurable to meet a variety of serial communication applications. The 20 Mbit/s data rate and multi-protocol support make it ideal for use in today's dynamic environment of changing specifications and increasing speeds. Numerous programmable features allow users to adjust device response to meet system requirements and accommodate future requirements. The IUSC contains a variety of complex internal functions, including two baud rate generators, a digital phase-locked loop, character counters, and 32-byte FIFOs for the receiver and transmitter.
An on-chip DMA channel allows high-speed data transfers from the receiver and transmitter. IUSC supports automatic status and control transfers via DMA and allows initialization of the serial controller under DMA control. Each DMA channel can complete 16-bit transfers in three 50ns clock cycles and can generate addresses compatible with 32-bit, 24-bit or 16-bit memory ranges. A DMA channel can operate in any of four modes: single buffer, pipeline, array chain, or linked list. Array chain and linked list modes provide scatter read and gather write capabilities with minimal software intervention. To prevent the DMA from holding bus mastery for too long, the mastership time can be limited by counting the absolute number of clock cycles, the number of bus transactions, or both.
The CPU bus interface is designed to work with any legacy multiplexed or non-multiplexed bus from CISC and RISC processor manufacturers including Intel, Motorola, and Zilog. The bus interface can be configured for 16-bit data, 8-bit data, individual addresses, or 8-bit data without individual addresses to support multiplexed or non-multiplexed buses.
IUSC handles asynchronous formats, synchronous bit-oriented formats such as HDLC, and synchronous byte-oriented formats such as Bisync and DDCMP. This device supports almost any serial data transfer application.
IUSC can generate and check CRC in any synchronization mode. Full access to the CRC value allows system software to retransmit or manipulate the CRC as needed by different applications. IUSC also provides equipment for modem control signals. In applications that do not require these controls, modem control can be used for general purpose I/O.
Interrupts are supported by a daisy-chain hierarchy within the serial channel and between the serial channel and the DMA. In serial controllers and DMAs, separating interrupt vectors for each interrupt type helps to quickly identify the source of the interrupt. IUSC supports pulse, double pulse and status interrupt acknowledgement cycles.
Supporting tools help designers program the IUSC efficiently. The technical manual describes all features in detail and gives programming sequence hints. The Electronic Programmer's Manual, DC 8287-02, is an MS-DOS, disk-based programming initialization tool that can generate custom sequences. In addition, Zilog offers a variety of application notes and development boards to help designers with hardware and software development. For more information, please contact your nearest Zilog representative.
Note: All signals with "/" before the front slash are active low signals, such as: b//w (word active low); /b/w (byte active low).
Follow these general instructions for power connections:
Connection circuit device power supply VCC VDD ground GND VSS

Pin description
The Z16C32 68-pin PLCC pin assignment shows the logical pin grouping of the IUSC pins that can only activate one strobe pin (/ds, /rd, /wr or pulse input) at a time. Any unused input pins (inputs when IUSC is a bus master or slave) must be pulled to their inactive state.
reset reset(input, active low). A low on this line places the IUSC in a known inactive state and conditions it so that data from the next assertion/write operation of the cs pin goes into the Bus Configuration Register (BCR) without Consider register addresses. / Reset should be lowered as soon as possible during power-up and as needed when the entire system or communications subsystem is restarted.
Clock System clock (input). This signal is the timing reference for the DMA and bus interface logic. (The serial controller portion is clocked by selected receive and transmit clock sources.)
Address/Data bus (input/tri-state output). After reset, these lines transfer data between the controlling microprocessor and the IUSC, as well as multiplexed addresses for registers within the IUSC. This operation between the host processor and the IUSC is often referred to as slave mode. These lines also transfer multiple addresses and data between the IUSC and system memory once the software has set up the device and put it into operation; this operation is called master mode. The AD15-0 can be used in a number of ways depending on whether the IUSC senses active on/off after reset and data written to the Bus Configuration Register (BCR).
Cesium chip select (input, active low). A low value on this line indicates that the current bus cycle controlling the microprocessor refers to a register in the IUSC. IUSC ignores /cs when low on/on indicates that the current bus operation is an interrupt acknowledgement cycle. On a multiplexed bus, iusc latches the state of the pin on a rising edge on /as; on a non-multiplexed bus, it latches on a rising/falling edge on /ds, /rd, or /wr /cs.

Read strobe (input/tri-state output, active low). This row represents read cycles on the bus for host processors/buses with such signals. When the IUSC controls the bus and operates in master mode, it is an output, otherwise, it is an input qualified by /cs low or /intack low. For the main read cycle, the IUSC captures data on the rising (trailing) edge of the row. For a slave read cycle, IUSC provides valid data on the AD line for the specified access time after the line goes low and holds the data valid until the master releases the line high.
Write strobe light (input/tri-state output, active low). This line represents a write cycle on the bus for the host processor/bus with such a signal. When the IUSC controls the bus and operates in master mode, it is an output, otherwise it is a /cs low qualified input. For a slave write cycle, the IUSC captures the write data on the rising (trailing) edge of the row. For the main write cycle, the IUSC places valid data on the AD line, then drives this signal low, and holds the data valid until this line is driven back high.
Byte/word selection (tri-state output, high indicates 8-bit transfer). When the IUSC controls the bus and operates as the master system, the high-order bits of this line indicate that one byte is to be transferred, and the low-order bits indicate that 16 bits are to be transferred. During a slave loop, the IUSC ignores this signal: it gets the byte/word difference from the AD line on the rising edge of /as, or from a bit in the serial or DMA command/address register.
Wait for wait, prepare or confirm handshake (input/tri-state output, active low). This line is an input when the IUSC controls the bus and operates in master mode. For slave loops, IUSC will activate the row as output. In both directions, the lines can carry wait or acknowledge signals depending on the state of the S//D input during the initial BCR write. If S//D is high when writing the BCR, this line runs as a ready/wait line for Zilog and most Intel processors. In this mode, the IUSC will not complete the main loop when the line is low, and it will assert the line low until it is ready to complete the interrupt acknowledgement loop; it never asserts the line when the host accesses one of the IUSC registers Row.
If S//D is low when writing the BCR, the line then runs as a confirmation line for Motorola and some Intel processors. In this mode, the IUSC will not complete the main cycle until this line is low. When it is ready to complete an interrupt acknowledgement cycle, it asserts the behavior register read and write cycle low.

For slave loops, this is a full-time (totem pole) output. Board Designer can combine this signal with similar signals from other slave systems via external logic gates or tri-state or open collector drivers.
Interrupt request (output, active low). When (1) its IEI pin is high, (2) one or more of its interrupt conditions are enabled and pending, and (3) its highest priority enabled/suspended condition or any higher priority internal condition is not The IUSC drives this line low when the in-service flag is set. Software can program the bus interface to drive this pin as a totem pole or open drain.
Interrupt acknowledgement (input, active low). A low value on this line indicates that the host processor is executing an interrupt acknowledgement loop. In some systems, a low value on this line may further indicate that external logic has selected this IUSC as a device to acknowledge, or as a potential device to acknowledge. A field in the bus configuration register selects whether the line carries a level-sensitive "status" signal, whether the IUSC should sample on the leading edge of /as or /ds, or whether it is a single-pulse or double-pulse protocol. As described in the text, the IUSC responds to the interrupt acknowledgement loop in various ways, depending on this programming and the state of the /int and iei lines.
Interrupt enable input (input, active high). This signal and the IEO pin can be part of an interrupt acknowledgement daisy chain for use with other devices that may request interrupts. If IEI is high outside of an interrupt acknowledgement cycle, one or more IUSC interrupt conditions are enabled and pending, and the under-service flag is not set to the highest priority condition or any higher priority condition, the IUSC passes its /int The pin is driven low to request an interrupt. If the IEI pin is high during the interrupt acknowledgement cycle, one or more IUSC interrupt conditions are enabled and pending, and the under service flag is not set for the highest priority condition or any higher priority, the IUSC holds IEO low and responds cycle.
Interrupt enable output (output, active high). This signal and/or IEI can be part of an interrupt acknowledgement daisy chain for use with other devices that may request interrupts. When the IEI pin is low, and/or the in-use flag is set in any case, the IUSC drives its IEO pin low. During the interrupt acknowledgement cycle, this IUSC drives this signal slightly differently, since it also forces IEO low if it (already) requests an interrupt.

Pin Description (Continued)
Basslake bus request (output, active low). The DMA controller section drives this line low to request control of the host bus. / Depending on a bit in the bus configuration register, BusReq can be an open-drain or resettable output. In open-drain mode, the IUSC samples the pin as an input and drives it low only after sampling.
/bin bus acknowledgment input (input, active low). When the IUSC receives a falling edge on this input, it samples whether it is driving (or just started driving)/busreq. If so, it will hold/approximately high and control the host bus. If not, subsidize the bus through low travel/approximately low travel. This signal can be used with /bout to form a bus authorization daisy chain for arbitration of bus control. Alternatively, it can be connected to the direct positive delegation of the external arbitrator, and the /bout-pin can be left unconnected.
/round bus ack output (output, active low). As mentioned above, this signal can be used with /bin to form a bus authorization daisy chain for arbitration of bus control.
/abort Aborts the main loop (input, active low). During the main loop, a low value on this line causes the currently active DMA channel to terminate its activity and enter a disabled state. Note that /abort is only valid during a DMA cycle, so IUSC knows which channel should abort. Also note that the external logic must set /wait//rdy to the correct state before /abort takes effect in order to complete the loop.
Receive data (input, positive logic). serial input.
Transfer data (output, positive logic). serial output.
Receive clock (input or output). This signal can be used as a clock input for any functional block in the serial controller. Alternatively, software can program the iusc so that this pin is an output with multiple receivers or an internal clock signal, a general purpose input or output, or an interrupt input.
Send clock (input or output). This signal can be used as a clock input for any functional block in the serial controller. Alternatively, software can program the iusc so that this pin is an output containing any of several transmitter or internal clock signals, a general purpose input or output, or an interrupt input.
Receive DMA requests (input or output). In device testing or in applications that do not use both the serial controller and DMA controller parts in the usual way, this pin can carry low dynamic DMA requests from the receive FIFO. On the IUSC, the request is internally routed to the on-chip receive DMA channel; typically the RxREQ pin is used as a general purpose output or interrupt input.
Transfer DMA request (input or output). In device testing or in applications that do not use both the serial controller and DMA controller parts in the usual way, this pin can carry low dynamic DMA requests from the transmit FIFO. On the IUSC, the request is internally routed to the on-chip transmit DMA channel, typically using the RxREQ pin as a general purpose output or interrupt input.
Data carrier detect (input or output, active low). Software can program the IUSC to enable/disable the receiver with this signal. Additionally, software can program the device to request an interrupt in response to a transition on this line. Pins can also be used as simple inputs or outputs.
Clear to send (input or output, active low). Software can program the IUSC to enable/disable the transmitter with this signal. Additionally, software can program the device to request an interrupt in response to a transition on this line. Pins can also be used as simple inputs or outputs.

port 7/txFutt
General purpose I/O or transfer COM
Platt (input or output). Software can program the IUSC to make this pin a general-purpose input or output, or to carry the complete signal from the transmitter to control an external driver. IUSC captures transitions on this pin in an internal latch.
PoT6/FSYNC
General purpose I/O or frame sync (input or output). Software can program the iusc to make this pin a general-purpose input or output or frame sync input for the iusc's time slot assignment circuit. IUSC captures transitions on this pin in an internal latch.
PORT5/RXSENC
General purpose I/O or receive synchronization (input or output). Software can program the IUSC to make this pin a general-purpose input or output, or to carry the receive sync output from the receiver. IUSC captures transitions on this pin in an internal latch.
PORT4/TXTSA
General purpose I/O or transmit slot allocation gate (input or output). Software can program the IUSC to make this pin a general-purpose input or output, or to carry the gate output of the transmit slot allocator, enabling an external TXD driver in slotted ISDN or fractional T1 applications. As mentioned in the text, IUSC captures transitions on this pin in an internal latch.

Port 3/RXTSA
General purpose I/O or receive slot allocation gate (input or output). Software can program the IUSC to make this pin a general-purpose input or output, or to carry the gate output of the receive slot allocator. IUSC captures transitions on this pin in an internal latch.
port 2
General purpose I/O (input or output). Software can program the IUSC to make this pin a general-purpose input or output. IUSC captures transitions on this pin in an internal latch.
Port 1-0/CLK 1-0
General purpose I/O or reference clock (input or output). Software can program the IUSC to make either of these pins a general-purpose input or output, or a reference clock that can be divided down to obtain the receiver and/or transmitter clock. When one of the pins is a general purpose I/O, the IUSC captures transitions on it in an internal latch.
power and ground. Each power rail contains seven pins, ensuring good signal integrity, preventing transients on the output, and improving noise margin on the input. The IUSC's internal power distribution network requires all of these pins to be properly connected.

architecture
The IUSC integrates a fast and efficient dual-channel DMA and a highly versatile serial communication controller. The functional capabilities of IUSC are described from two different perspectives; as a data communication device, it transmits and receives data in various data communication protocols; as a microprocessor peripheral device, it has two DMA channels and provides the following functions:
Four DMA transfer types, flexible bus interface and vectored interrupts. The architecture is divided into three parts: DMA and bus interface capabilities, communication between DMA and serial channels, and serial communication capabilities

DMA and bus interface functions
The IUSC's two general-purpose DMA channels combined with a flexible bus interface allow it to meet various application needs. The time required to move data in and out of the transmitter and receiver is minimized by the speed of the IUSC (20 MHz clock, three clock cycles per word, typically); two buffer chain modes with linked frame status transfers; Early buffer termination that keeps received frames in separate memory buffers; and vectored interrupts. Some of these features are briefly described below, but users should refer to the IUSC Technical Manual for more information.
DMA method
The IUSC contains two DMA channels, one for the transmitter and one for the receiver. Each channel supports 32-bit addresses and 16-bit byte counts. Channels operate in one of four modes. In normal mode, the processor must reload the address and length at the end of each buffer. In pipelined mode, the processor can load the address and length of the next buffer at any time during the DMA transfer to the first buffer. In array chain mode, the processor creates a table of address/length pairs in memory for automatic transmission by the channel. In linked list mode, the processor creates a linked list of address and length pairs in memory, which is automatically transmitted by the channel.
Single-buffer mode is the most basic of the four types of data transfer. The starting address of each memory buffer and the maximum number of characters to be transferred to or from memory are programmed into the IUSC register. When DMA is enabled, it transfers all data between system memory and the transmit and receive FIFOs.
Pipeline mode is similar to single buffer mode, it adds a set of registers into which the processor can load the address and count of the next memory buffer to reload the DMA. So when one buffer is done, IUSC is pre-programmed with the address and count of the next buffer so that the DMA doesn't need to stop between each buffer as long as the software is one step ahead of the memory buffer usage.
In array mode, one of two linked modes, the software builds a memory buffer information table. The length of the array is only limited by the amount of system memory available to the buffer. IUSC is programmed with the buffer address and the location of the size array. The advantage of this mode is that fewer bursts of short frames may exceed the tracking capability of the system. The use of receive status blocks and transmit control blocks and early buffer termination simplifies the splitting and reassembly of serial messages in memory buffers. When a dma channel gets a buffer count of zero, it stops and can create an array end interrupt.
Linked list mode is the most common DMA mode. It has the ability to quickly switch buffers in array mode without requiring the buffer information to be in a contiguous table. Each link entry contains: the starting address for writing or reading data; the size of the buffer; optional status or control information; and a pointer to the next link. Memory buffers can easily be added and removed by changing the link in the list item.
DMA Features In linked list mode, the IUSC has a programmable feature to facilitate the use of buffers in the ring. When this feature is enabled, the DMA writes zeros back to its buffer length field after each array or list item has been read. So if a linked list wraps around itself, the DMA channel will not reuse the buffer until software has processed it, and by writing a non-zero value in the count field (getting a zero-valued count value will stop the with a DMA channel) to indicate that it is eligible for reuse. This function can also be used to trace buffer usage in array mode.
In bus slave and master modes, the IUSC can read and write data words in any byte order. It supports the little endian convention used by many Intel microprocessors and the big endian convention used by many Motorola microprocessors. When the IUSC is the bus master, it can be programmed to generate only the upper 16-bit address when needed, saving one clock cycle per transfer (three clocks per transfer instead of four). When using iusc on a 16-bit bus, the starting address of the message is an odd-numbered address, and the iusc automatically relocates itself to an even-numbered boundary by fetching a byte first. This is especially important when the retransmitted header size is different from the received header size. Two pins can be used as status signals of the type of transfer in progress.
There are various commands and status registers to control and monitor DMA channels. The DMA channel can be aborted by the /abort pin or a software command. The pause command can also be used to temporarily pause transfers

The bus interface and the use of the bus interface module are located between the external bus pins and the on-chip 16-bit data bus interconnected with other functional modules. It includes several flexible bus interface options, controlled by the contents of the Bus Configuration Register (BCR). The BCR is the destination where the host processor first writes to the IUSC after reset.
IUSC is compatible with multiplexed and non-multiplexed bus interfaces and can transmit 8-bit or 16-bit. It supports data transfer in either format using the /rd and /wr or r//w and /ds strobe pins and byte order. IUSC generates the wait or ready confirmation handshake used by Intel or Motorola microprocessors. Additionally, three types of interrupt acknowledgement signals are supported for automatic return of the interrupt vector to any general purpose microprocessor.
There are several options that control how the IUSC uses the bus. The /bin and /bout pins can be used to form a bus authorization daisy chain. The IUSC has several options on how to arbitrate bus master requests between channels and how long to leave the bus between requests. The priority of the two DMA channels is programmable and can be alternated between requests to allow both channels to access the bus equally. Once one of the channels has mastered the bus, if control is requested, control can be passed to the other channel, or the IUSC can be forced off the bus. The programmable preemption feature selects whether a higher-priority channel can take control of the bus if it begins to request control while a lower-priority channel is using the bus.
The IUSC keeps /BUSREQ active until the transmit FIFO is full, the receive FIFO is empty, or both, thus making the most of its 32-byte FIFO. A programmable dwell timer can be used to limit the time the IUSC remains in bus master state by counting bus transfers, clock cycles, or both. Therefore, the combination of programmable FIFO request levels, channel arbitration options, and programmable resident timer functionality provides application software flexibility to optimize IUSCS bus occupancy to meet system throughput and bus response requirements.
interrupt
IUSC's interrupt subsystem is derived from Zilog's experience in providing state-of-the-art interrupt capabilities in the microprocessor field. These features are best when used with ZiLog microprocessors, but it is also easy to interface the IUSC with other microprocessors. Four pins are dedicated to creating interrupt daisy-chain hierarchies within serial channels and between serial channels and DMA.
When the IUSC responds to an interrupt acknowledgement from the CPU, it places an interrupt vector on the data bus. To speed up interrupt response time, IUSC modifies three bits in the vector to indicate the requested interrupt type. Separate vectors are provided for serial channels and DMA to facilitate differentiation of interrupt sources.
DMA has four interrupt sources for receive and transmit channels. Each interrupt source is enabled independently, and all DMA interrupts have a master enable. The four interrupt sources are end of array/end of link, end of buffer, hardware abort and software abort.
Of the six interrupt types in the serial section IUSC (receive status, receive data, transmit status, transmit data, I/O status, and device status), each has three bits associated with it: Interrupt Pending ( IP), Interrupt in Service (IUS) and Interrupt Enable (IE). If the IE bit is set for a given source, then this bit can source request interrupts. Note that each source of the six types also has its own interrupt arm bit. Finally, there is a Master Interrupt Enable (MIE) bit, which globally enables or disables all interrupts from the serial channel.
Interrupt (/int), Interrupt Acknowledge (/intack), Interrupt Enable Input (iei), and Interrupt Enable Output (ieo) pins are provided to create an automatic mechanism to place vectors on the bus with the highest priority of multiple devices on the bus interrupted. The device with the highest pending interrupt (/int low, iei high) places a vector on the bus in response to an interrupt acknowledge cycle.
In IUSC, the IP bit indicates that an interrupt is pending. If an IUS bit is set, the interrupt will be serviced and all low priority interrupt sources will be blocked from requesting an interrupt. An IUS bit is set during the interrupt acknowledgement cycle if no higher priority device requests an interrupt.

DMA and bus interface capabilities (continued)
There are six receive status interrupt sources. Each is individually armed: Receiver out of hunt, Idle line received, Interrupt/Abort received, Code Collision/End of transmission/End of message received, Parity error/Abort and Overrun error. A receive data interrupt is generated whenever the receive FIFO is filled with data beyond the level programmed in the receive interrupt control register (RICR). There are six sources of transmission status interrupts. Each is individually guarded: Transmit Preamble, Transmit Idle Line, Transmit Abort, Transmit End of Frame/Message, Transmit CRC, and Underrun Errors. A transmit data interrupt is generated when the transmit FIFO is emptied below the level programmed in the Transmit Interrupt Control Register (TICR).
The I/O status interrupt is used to report transitions on any of the six pins. Generate interrupts on either or both edges, each with individual edge selection and configuration. The pins that can be programmed to generate I/O status interrupts are /RXC, /TXC, /RXREQ, /TXREQ, /DCD, and /CTS. These interrupts are independent of the pin's programmed function.
The device status interrupt has four individually enabled sources: receive character counter underflow, fetched dpll sync, brg1 zero count, and brgo zero count. See the IUSC Technical Manual for more details.
Communication between DMA and Serial Channels IUSC's on-chip communication between DMA and serial communication controllers provides the ability to achieve higher efficiency than a separate DMA controller. The linked frame status transfer function writes the status and byte count of each received frame to memory as part of an array or linked list. This provides an easy-to-use mechanism to store the results of received messages without placing arbitrary restrictions on how fast the host software can examine the results. Likewise, control information for a transfer frame can be automatically read from the array or link by the DMA and transferred to registers in the serial logic.
In all modes, the DMA can accept signals from the serial channel to prematurely terminate the buffer. When the end of the message is received, the data is transferred to the buffer and the state is written to memory. If linked frame state transfer is enabled, state will be written after data in single buffer and pipe modes, or array/linked in array and linked list modes. This early buffer termination is the same as the terminal count condition in DMA. Therefore, receiving the end of the message is a seamless transition from one memory buffer to the next.
Figure 5 shows an example of using these interactive features using the linked list pattern. This example shows the format of a memory buffer ring with link frame state transfer and ring buffer features enabled. Any protocol (like hdlc or 802.3) with the "rxbound" bit set (rcsr4=1) will work for this example. For simplicity, the linked list is shown in Figure 5, with three links, and can be as large as possible in memory. The sixth word in each list item is reserved and should not be used (it keeps list items on 32-bit boundaries). If the end of the buffer is reached, not the end of the frame, IUSC writes zeros as the status and count. Also, if the transfer channel needs to start a new memory buffer other than at the beginning of the frame, the DMA ignores the transfer control block.

Another way DMA and serial channels work together is to use a transfer character counter to break up a chunk of data into fixed-length frames. For example, a large file located in multiple memory buffers needs to be transferred as smaller fixed-length frames. With IUSC, the serial channel is programmed to send an end-of-frame sequence with a set number of bytes per transfer. Therefore, DMA transfers are not interrupted and no system response is required to break large files into frames.
Compared to discrete serial and DMA chip solutions, IUSC provides higher throughput because discrete chips do not communicate directly, so the state of one device must be read by the CPU and communicated with another device. This usually requires interrupting and pausing the activity until the status/control information is updated. This will use precious time and bus bandwidth, limiting overall throughput.

data communication capability
IUSC provides a programmable full-duplex channel for any common data communication protocol. The receiver and transmitter are completely independent, each supported by a 32-byte deep FIFO and a 16-bit frame length counter. All modes allow optional even, odd, mark or space parity. Synchronous mode allows the choice of two 16-bit or 32-bit CRC polynomials. Character lengths of up to 8 bits are individually programmable for the receiver and transmitter. Data in the receive FIFO carries error and status conditions to greatly reduce the CPU overhead required to send or receive messages, while key control parameters accompany the transmitted characters through the TX FIFO. Interrupts can be individually set to signal states such as Overrun, Parity Error, Frame Error, End of Frame, Receive Idle Line, Sync Acquisition, Transmit Underrun, Transmit CRC, Transmit Off Sync/Flags, Transmit Abort, Transmit Idle Line and Transmit Prefix. Additionally, some useful internal signals, such as Receive Character Boundary, Receive Sync, Transmit Character Boundary, and Transmit Complete, can be sent to the pins for use by external circuits.
Protocol asynchronous mode. The receiver and transmitter process data at 1/16, 1/32 or 1/64 of the clock rate. The receiver rejects start bits less than half a bit time and includes recovery logic after framing errors. The transmitter is capable of sending one, two, or anywhere in the range of 9/16 to 2 stop bits per character in 1/16-bit increments.
Nine-bit mode. This mode is the same as asynchronous mode, except that the receiver checks the state of the additional address/data bits between the parity and stop bits. The value of this bit is configured along with the data. In the transmitter, this bit is automatically inserted into the FIFO value of the transmitted data.
isochronous mode. Both the transmitter and receiver operate on start-stop (asynchronous) data using the 1X clock. The transmitter sends one or two stop bits.
Asynchronous with code conflicts. This is similar to isochronous mode, except that the start bit is replaced by a three-bit timecode violation mode, as described in mil-std1553b. The transmitter sends zero, one or two stop bits.
HDLC mode. In this mode, the receiver recognizes the flag, performs optional address matching, accommodates extended address fields, and performs zero deletion and CRC checking. The receiver can receive the sharedzero flag, identify the abort sequence, and can receive frames of any length. The transmitter automatically transmits on and off flags, performs zero insertion, and can be programmed to transmit aborts, extended aborts, flags or CRC, and flags on transmit underrun. At the end of the programmed message length, the transmitter automatically sends a close flag with an optional CRC. Select the sharedzero flag in the transmitter and program a separate character length for the last character in the frame.
In addition to status interrupts that can be enabled, frames terminated with an abort can also be marked with a status bit on the preceding character. Aborts are only detected in frames, thus eliminating false detections due to idle lines. IUSC provides four line preamble options (flags, all 1s, all 0s, or alternating 1s and 0s) to condition the line before starting data transmission. This feature is valuable for synchronizing the receiver DPLL and as a flow control mechanism to slow down frame transfers without slowing down the clock or disabling the transmitter.
HDLC loop mode. This mode is only available in the transmitter and allows IUSC to be used in an HDLC loop configuration. In this mode, the receiver is programmed to operate in HDLC mode to allow the transmitter to echo back received information. Once a specific bit pattern (actually seven consecutive sequences) is received, the transmitter stops repeating the data and inserts its own frame.
802.3 mode. This mode implements the IEEE 802.3 data format using 16-bit address comparison. In this mode, /dcd and /cts are used for carrier sensing and collision detection to interact with receivers and transmitters. Backoff time must be provided externally.
single modal. In this mode, a single character is used for synchronization. The sync character can be 8 bits long or the same length as the data character. The receiver can automatically remove sync characters from the received data stream. The transmitter is programmed to automatically send a CRC on underrun or at the end of the programmed message length.
slaved single-sync mode. This mode is only available in transmitters and allows the transmitter (operating as if in single-sync mode) to send data whose byte boundaries are synchronized with the byte boundaries of the received data.
Dual mode. This mode is the same as the single sync mode, except that character synchronization requires two consecutive characters.

Transparent double sync mode. In this mode, the synchronization mode is DLE-SYN, which is programmable and can be selected from ASCII or EBCDIC encoding. The receiver recognizes the sequence of control characters and handles the CRC calculation automatically without CPU intervention. The transmitter is programmed to send SYN, DLE-SYN, CRC-SYN, or CRC-DLE-SYN on underrun, and automatically send a closed DLE-SYN with optional CRC at the end of the programmed message length.
External sync mode. The receiver is synchronized with the received data via an externally provided pin signal for custom protocol applications.
data encoding
The IUSC is programmed to encode and decode serial data in eight different ways (Figure 6). The choice of the transmitter encoding method is independent of the receiver decoding method.
NRZ. In nrz, a 1 is represented by a high level for the bit cell duration and a 0 is represented by a low level for the bit cell duration.
NRZBnrzb is reversed from nrz.
NRZI Mark. In the nrzi flag, a 1 is represented by a transition at the beginning of a bit cell, ie a level reversal present in the previous bit cell. 0 means that the bit cell started with no transition.
NRZI space In nrzi space, 1 means that the bit cell starts with no transition, i.e. maintains the level present in the previous bit cell. 0 is represented by a transition at the beginning of the bit cell.
Biphase Mark. In biphase notation, a 1 is represented by one transition at the beginning of the bit cell and another transition at the center of the bit cell. 0 is only represented by a transition at the beginning of a bit cell.
Biphasic space In biphasic space, 1 is only represented by the transition at the beginning of the bit cell. 0 is represented by a transition at the beginning of the bit cell and another transition at the center of the bit cell.
Biphase Level. In biphasic levels, a 1 is represented as a high level for the first half of the bit cell and a low level for the second half of the bit cell. A 0 is represented by a low in the first half of the bit cell and a high in the second half of the bit cell.
Differential two-phase level. In differential biphasic levels, a 1 is represented by a transition at the center of the bit cell with the opposite polarity to the transition at the center of the previous bit cell. 0 is represented as a transition at the center of the bit cell with the same polarity as the transition at the center of the previous bit cell. In both cases, there are transitions at the beginning of the bit cells to set the level required for proper center transitions.

Data Communication Capability (continued)
character counter
The IUSC contains separate 16-bit character counters for the receiver and transmitter. The receive character counter is set to a programmable start value, or automatically at the beginning of each received frame, and can be reloaded under software control during the frame. The counter is decremented for each received character. At the end of a received message, the current value in the counter is automatically loaded into a four-deep FIFO. When the Receive Status Block (RSB) function is enabled, the counter value and status (RCSR) can be automatically transferred to the memory after the data. In array and linked list modes, RSBs can be transferred to array or list entries for easy software access. This allows the DMA transfer of data to continue at the end of the received frame without CPU intervention, as the values in the FIFO allow the CPU to determine the status and length of each frame.
Likewise, the transmit character counter is automatically loaded at the beginning of each transmit frame and can be reloaded under software control during the frame. The counter is decremented with each write to the transmit FIFO. When the counter reaches zero, and that byte is sent, the transmitter automatically terminates the message in an appropriate manner (usually by sending a CRC and a close flag or sync character) without CPU intervention. In linked list and array mode, the number of transmitted characters and frame control word can be extracted from the linked list or array.
baud rate generator
IUSC contains two baud rate generators. Each generator consists of a 16-bit time constant register and a 16-bit down counter. In operation, the counter is decremented with each cycle of the selected input clock, and the time constant can be automatically reloaded when the count reaches zero. The output of the baud rate generator switches when the counter reaches half the time constant and again when the counter reaches zero. A new time constant can be written at any time, but the new value will not take effect until the next load of the counter. The outputs of the two baud rate generators are sent to a clock multiplexer for internal or external use. The input for the baud rate generator can be the /txc pin, the /rxc pin, the port pin, or the output of any counter. The output frequency of the baud rate generator is related to the input clock frequency of the baud rate generator, and the formula is as follows:
Output frequency = input frequency / time constant + 1.
Note: This allows the output frequency to be in the range of 1 to 1/65536 of the input frequency, inclusive.
The output of the baud rate generator can be used as a transmit or receive clock, a reference clock input to the DPLL circuit, and/or output on the /rxc or /txc pins.
digital phase locked loop
The IUSC contains a DPLL (Digital Phase Locked Loop) that recovers clock information from the data stream using NRZI or biphase encoding. The DPLL is driven by a clock that is typically 8, 16 or 32 times the receive data rate. The DPLL uses this clock and the data stream to construct the clock for the data. This clock can be routed to the receiver, transmitter, or both, or to a pin for external use. In all modes, the DPLL calculates the input clock to create the nominal bit time. While counting, the DPLL monitors the incoming data stream for transitions. When a transition is detected, the DPLL can make a count adjustment (within the next count cycle) to generate an output clock that tracks the input bit cells. The DPLL provides the appropriate phase transmit and receive clocks to the clock multiplexer.
counter
The IUSC contains two 5-bit counters programmed to divide the input clock by 4, 8, 16 or 32. The outputs of these two counters are sent to the clock multiplexer. The counter can be used as a prescaler for the baud rate generator. While the DPLLs provide the receive clock, they also provide a stable transmit clock from a common source. The pins of port 0 and port 1 can be used as the input of the counter.

Clock Multiplexer The clock multiplexer logic selects the receive and transmit clocks and optional outputs on the /rxc and/or /txc pins. In the Z16C32, the pins of port 0 and port 1 can be directly used as receive and transmit clocks, and can also be used as counter inputs.
time slot allocation procedure
The IUSC is equipped with two slot allocators to support ISDN and fractional T1 communications. The receiver has an allocator. Each slot allocation procedure selects one or more slots within a frame, however, the selected slots must be consecutive. The first selected slot can be programmed from slot 0 (the first slot) to slot 127 of the frame. The number of connection slots can be programmed from 1 to 15 (total slots). The time of the first slot can be shifted by an integer number of clocks. This offset is a delay programmable from 0 (no offset) to 7 clocks in increments of one clock (one bit cell). This offset can be used to compensate for delays in the frame sync detection logic.
test mode
The IUSC can be programmed for local echo or auto echo operation. In a local loopback, the sender's output is internally routed to the receiver's input. This allows the IUSC datapath to be tested without any external logic. Auto Echo connects the RxD pin directly to the TXD pin. This is useful for testing serial links outside the IUSC.
I/O port pins are general purpose I/O pins. They are used as additional modem control lines or other I/O functions. Each port bit is individually programmable as a general-purpose input, output, or dedicated input or output function. This programming is done in the port control registers. Port pins can be read at any time, whether used as input or output.
Dedicated functions of port pins include slot allocation gate output, transmit complete output, clock input, receive sync output, or frame sync input.
Port pins capture edge transitions. The programming of capture is done using the port latch/unlock command bits in the port status register. Each port bit is individually controlled. The latch/unlock bit is used as a status signal to indicate that a transition has occurred on the port pin, and as a command to open a latch that captures this transition. Detect rising and falling edges. When a transition is detected, the latch closes, maintaining the post-transition state of the input.
The lock/unlock bit remains at 0 if no transition has occurred on the port pin; when a rising or falling transition is detected, the bit is set to 1; if one or more transitions occurred while the latch was off, the Set to 1 immediately after the lock is opened. Writing a 0 to the latch/unlock bit has no effect on latching. Writing a 1 to this bit will reset the status bit and open the latch. To use the port as an input without edge detection, write 1 to the latch/unlock bit to turn on the latch, then read the port status register to get the current pin input state.

Programming Electronic Programmer's Manual (MS-DOS-based) and Technical Manual are available to provide detailed information on IUSC programming. Also includes explanations and characteristics of all registers in IUSC.
The system programs the registers in the IUSC to configure the channel. Before this can happen, the system must set up the bus interface by writing to the Bus Configuration Register (BCR). The BCR has no specific address and can only be accessed after a device hardware reset. After hardware reset, write IUSC for the first time to program BCR. From then on, other channel registers can be accessed. There is no need to provide the IUSC with a specific address for BCR writes; the IUSC knows that the first write after a hardware reset is to the BCR.
In the case of a multiplexed bus, all registers are directly addressable via addresses latched by /as at the beginning of each bus cycle. The D//C pins are still used to directly access the receive and transmit data registers (RDR and TDR) over the multiplex bus; if D//C is high, the address locked by /AS is ignored and an RDR or TDR access is performed.
In the non-multiplexed bus case, the channel registers are accessed indirectly using the address pointer in the Channel Command/Address Register (CCAR). The address of the desired register is first written to the CCAR, then the selected register is accessed; after this access, the pointer in the CCAR is automatically cleared.
There are two other things to note about the IUCN. The channel reset bit in CCAR puts the channel in a reset state. To exit this reset state, either write a word of all zeros to the CCAR (16-bit bus), or write a byte of all zeros to the lower byte of the CCAR (8-bit bus). Second, after reset, the transmit and receive clocks are disabled. The first thing to do in any initialization sequence is to write to the Clock Mode Control Register (CMCR) to select the receiver and transmitter clock sources.
Serial/DMA (S//D) pins are used to differentiate between serial channels and DMA registers. The DMA registers are divided into three logical groups: common registers that apply to transmit and receive, transmit registers, and receive registers. The registers for the DMA transmit function and receive function are symmetrical, therefore, in the following pages, a diagram is shown for each register. When addressing DMA registers, the data/control (D//C) pins select between transmit and receive registers. For example, at address 10101 there is a DMA byte count register for transmit and receive (tbcr and rbcr) with its s//d pin low. TBCR is selected when D//C pin is low, RBCR is selected when D//C pin is high

Register Descriptions This section describes the functions of the various bits in the device registers. This section discusses the following conventions:
Control bits are written and read by the CPU and are not modified by the device. Command bits are written by the CPU to initiate operations in the device and read as zero. Status bits are controlled by the device and read to check the device status. The device will ignore any writes to the status bits. Command/status bits are controlled by the device and the CPU. They can be written and read by the CPU, and can also be modified by the device.
Reserved bits are not used for this implementation of the device and may or may not actually exist in the device. Any reserved bits that are physically present are both readable and writable, but reserved bits that are not present are always read as zeros. To ensure compatibility with future versions of the device, reserved bits should always be written with zeros. Reserved commands should not be used for the same reason.