Features

In-system programmable proms for configuring xilinx fpgas low power advanced CMOS or flash processing endurance of 20,000 program/erase cycles Operates over the full industrial temperature range (–40°C to +85°C) IEEE Std 1149 .1/1532 Boundary Scan (JTAG) support for programming, prototyping, and testing J-standard FPGA configurations with tag command initiation. Used to store longer or multiple bitstreams. Dedicated Boundary Scan (JTAG) I/O Power Supply (VCCJ): The I/O pins are compatible with voltage levels from 1.8V to 3.3V. Design support using Xilinx ISE Alliance and base packages
XCF01S /XCF02S/XCF04S 3.3V supply voltage serial FPGA configuration interface available in small form factor VO20 and VOG20 packages XCF08P/XCF16P/XCF32P 1.8V supply voltage serial or parallel FPGA configuration interface available in small form factor VOG48, FS48 and FSG48 packages Design revision Technology enables S storage and access to multiple design versions for configuration Built-in data decompressor compatible with Xilinx advanced compression technology

Description Xilinx introduces the platform flash series of programmable configuration proms in the system. Available in densities from 1 to 32MB , these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large XilinxFPGA configuration bitstreams. The platform flash PROM family includes the 3.3V XCFXS PROM and the 1.8V XCFXXP PROM. XCFxXS versions include 4 MB, 2 MB and 1 MB PROM, support serial master and slave serial FPGA configuration modes XCFxxp versions include 32 MB, 16 MB and support serial master, serial slave, master select map and slave select map FPGA 8 MB PROM in Configuration Mode When driven from a stable external clock, the PROM can output data at rates up to 33 MHz.

When the FPGA is in master serial mode, it generates a configuration clock that drives the programmable read-only memory. With CF high, data is available on the PROM data (D0) pin connected to the FPGA DIN pin for a short access time after CE and OE are enabled. New data is available within a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. Both PROM and PROM are clocked by an external clock source when the FPGA is in slave serial mode, or, for XCFxxp PROM, PROM can be used to drive PROM The configuration clock for the memory. The XCFxxp version of the Platform Flash Programmable ROM also supports Master Select Mapped and Slave Select Mapped (or Slave Parallel) FPGA configuration modes. When the FPGA is in master select map mode, the FPGA generates a configuration clock that drives the programmable read-only memory. When the FPGA is in slave select map mode, an external oscillator generates the configuration clock that drives the PROM and FPGA, or alternatively, the xcfxxp prom can be used to drive the configuration clock for the FPGA. In busy low and cf high states, data is available on the Proms data (D0-D7) pins when CE and OE are enabled. New data is available with a short access time after each rising clock edge. Data is clocked into the FPGA on subsequent rising edges of CCLK. In Slave Parallel/Slave Select Mapping mode, a free-running oscillator can be used. The XCFxxp version of the platform flash prom provides additional advanced features. The built-in data decompressor supports the use of compressed PROM files, and design modifications allow multiple design modifications to be stored on a single PROM or across multiple PROMs. For design revisions, external pins or internal control bits are used to select the active design revision. Multiplatform flash programmable ROM devices can be cascaded to support larger configuration files when targeting larger FPGA devices or targeting multiple FPGAs daisy-chained together. When using the advanced features of the xcfxp platform flash prom, such as design modifications, programming files across cascaded prom devices can only be created for cascaded chains that only contain the xcfxp prom. If the advanced xcfxxp feature is not enabled, the cascade chain can contain both xcfxxp and xcfxx prom.

Platform Flash Programmable ROM User Guide for a detailed guide on connecting the Programmable ROM to the FPGA configuration hardware, understanding software usage, and reviewing the reference list of Xilinx FPGAs and each compatible platform Flash Programmable ROM. Table 2 lists the platform flash prom and its capacity.
Programming Platform Flash Programmable Read-Only Memory is a reprogrammable NOR flash memory device. Reprogramming requires erasing and then performing program operations. It is recommended to perform a verification operation after the program is run to verify that the data transfer from the programming source to the platform flash programmable ROM is correct. There are several programming solutions available.
In in-system programming, system-programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol,
Provides fast and efficient design iteration in system programming and eliminates unnecessary packet processing or device socketing. The programming data sequence is transferred to the device using xilinx shock software and a xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates JTAG.
Instruction sequence of instructions. IMPACT software also outputs Serial Vector Format (SVF) files for use with any tool that accepts SVF format, including automated test equipment. During system programming, the CEO's output is driven high. During system programming, all other outputs remain in a high-impedance state or remain clamped. During system programming, all non-JTAG input pins, including CLK, CE, CF, OE/RESET, BUSY, ENU EXT USEL and REV USEL[1:0] are ignored. System programming is fully supported within the recommended operating voltage and temperature ranges. Embedded, in-system programming reference designs such as the Xapp058, Xilinx's use of embedded microcontrollers in in-system programming, are available on the Xilinx web page for PROM programming and data storage application notes. For an advanced update method using the design modification features in the platform flash xcfxxp proms, see the UG161 platform flash prom user guide. The 1/2/4 MB xcfxs platform flash proms in the oe/reset system programming algorithm cause an internal device reset to be issued, causing the oe/reset pulse to be low.
In a traditional manufacturing environment, third-party device programmers can program the platform flash prom with an initial memory image before assembling the prom on the board. Please contact your preferred third-party programmer vendor for platform Flash PROM support information. A sample list of third-party programmer vendors supporting platform Flash PROMs for use with third-party programmer device support is available on the Xilinx webpage. Refer to the UG161 Platform Flash PROM User Guide for the PROM data file format required by programmers. The pre-programmed PROM can be assembled onto the board using the typical soldering procedure guidelines in the UG112 Equipment Package User Guide. Using an in-system programming solution, the pre-programmed PROM memory image can be updated after board assembly.
Reliability and Endurance in System Programmable Products Xilinx guarantees an endurance level of 20,000 system program erase cycles and a data retention period of at least 20 years. Each device meets all functional, performance and data retention specifications within this endurance limit

Design Security The Xilinx Flash Programmable Read-Only Memory device in the System Programmable Platform includes advanced data security features to fully protect FPGA programming data from unauthorized reads via JTAG. The xcfxp proms can also be programmed to prevent accidental writes via jtag. Tables 3 and 4 show the security settings available for xcfxx-prom and xcfxxp-prom, respectively.
Read Protection The user can set the read protection security bit to prevent the internal programming mode from being read or copied by JTAG. Read protection does not block write operations. For xcfxs prom, setting the read-protect security bit for the entire device, resetting the read-protect security bit requires erasing the entire device. For XCFxxp programmable read-only memory, the read-protect security bits can be set for individual design modifications, and the overwrite-protected xcfxp prom devices also allow the user to write-protect (or lock) specific design revisions or prom option settings. Write protection helps prevent unintentional JTAG instructions from modifying the area by write-protecting the area and locking the erase command. The write-protect setting can be cleared by erasing the protected area. However, an xsc_unlock instruction must first be issued to the xcfxp prom to unlock the isc_erase instruction. See the xcfxp prom bsdl file for xsc_unlock and isc_erase instructions. Be careful! When performing an erase operation on an XCFxxp programmable ROM, affecting software always issues an XSC_Unlock and, therefore, always unlocks the write protection.

The IEEE1149.1 Boundary Scan (JTAG) Platform Flash Programmable Read-Only Memory family is compatible with the IEEE1149.1 Boundary Scan Standard and the IEEE1532 System Configuration Standard. Test Access Ports (TAPs) and registers are provided to support all required boundary scan instructions, as well as many optional instructions specified by IEEE Standard 1149.1. Additionally, the JTAG interface is used to implement in-system programming (ISP) to facilitate configure, erase, and verify operations on platform flash programmable read-only memory devices. Table 5 lists the platform flash promotions. For a full description of the Boundary Scan structure and required and optional instructions, be careful! The xcfxp jtag tap pause state is not fully compliant with the jtag 1149.1 specification. If the JTAG shift operation needs to be temporarily suspended, stop the JTAG TCK clock and keep the JTAG TAP in the JTAG SHIFT IR or SHIFT DR TAP state. Do not transition xcfxp jtag tap via jtag pause ir or pause dr tap state to temporarily pause jtag shift operations.

Instruction Register In the instruction scan sequence, the instruction register (IR) of the platform flash programmable read-only memory is connected between TDI and TDO. To prepare the instruction scan sequence, instruction registers are loaded in parallel in a fixed instruction capture mode. The pattern is shifted out to TDO (LSB first), and the instruction is shifted from TDI into the instruction register. xcfxs Instruction Register (8 bits wide) The instruction register (ir) of the xcfxs programmable read only memory is 8 bits wide and is connected between TDI and TDO during the instruction scan sequence. The detailed composition of the instruction capture mode is shown in Table 6 on page 6. Instruction capture modes moved out of the xcfxx device include ir[7:0]. IR[7:5] are reserved bits, set to logic 0. The ISC Status field ir[4] contains a logical 1 if the device is currently in System Configuration (ISC) mode; otherwise, it contains a logical 0. The security field ir[3] contains a logic 1 if the device is programmed with the security option turned on; otherwise, it contains a logic 0. IR[2] is unused and set to "0". The remaining bits ir[1:0] are set to "01" as defined by IEEE Standard 1149.1.
xcfxxp instruction register (16 bits wide) The instruction register (ir) of the xcfxxp prom is 16 bits wide and is connected between TDI and TDO during the instruction scan sequence. Instruction capture modes moved out of the xcfxxp device include ir[15:0]. IR[15:9] are reserved bits, set to logic 0. The isc error field ir[8:7] contains 10 when the isc operation succeeds; otherwise, it contains 01 when the in-system configuration (isc) operation fails. The Erase/Program (ER/PROG) error field ir[6:5] contains 10 when the erase or program operation is successful; otherwise, it contains 01 when the erase or program operation fails. The Erase/Program (ER/PROG) status field IR[4] contains a logic 0 when the device is busy performing an erase or program operation; otherwise, it contains a logic 1. The ISC Status field ir[3] contains a logical 1 if the device is currently in System Configuration (ISC) mode; otherwise, it contains a logical 0. The "Done" field ir[2] contains a logic 1 if the sampled design revision was successfully programmed; otherwise, a logic 0 indicates that the programming was incomplete. The remaining bits ir[1:0] are set to 01, as defined by IEEE Standard 1149.1.

Boundary Scan Registers Boundary scan registers are used to control and observe the state of device pins during extest, sample/preload, and clamp instructions. Each output on the platform flash prom has two register stages that contribute to boundary scan registers, while each input has only one register stage. There are three register levels for bidirectional pins, which act on boundary scan registers. For each output pin, the register stage closest to TDI controls and observes the output state, while the second stage closest to TDO controls and observes the high-Z enable state of the output pin. For each input pin, a register stage controls and observes the input state of the pin. Bidirectional pins combine three bits, first the input stage bit, then the output stage bit, and finally the output enable stage bit. The output enable level bits are closest to TDO. See Table 12 on page 24 and Table 13 on page 26 for the boundary scan bit order of all connected device pins, or see the corresponding BSDL file for the full boundary scan bit order description under the "Attribute Boundaries\Registers" section of the BSDL file. The bit assigned to boundary scan cell 0 is the LSB in the boundary scan register and is the register bit closest to TDO.
Identification Register idcode The register idcode is a fixed, vendor-specified value used to electronically identify the manufacturer and type of device being addressed. The width of the IDcode register is 32 bits. The idcode register can be shifted out for inspection using the idcode instruction. IDcode can be provided to any other system component via JTAG. The idcode register value of flash proms. IDcode registers have the following binary format:
User Code Registration The User Code command allows access to a 32-bit user-programmable scratchpad that is typically used to provide information about what to program the device. User programmable identification codes can be removed for inspection by using user code instructions. This code is loaded into the user code registers during programming of the platform flash programmable read only memory. If the device is empty or not loaded during programming, the user code register contains ffffffffh. The client code register of the xcfxp platform flash prom, in addition to user code, can also be assigned a unique 32-byte client code for each design version that the prom enables. Customer code is set during programming and is typically used to provide information about the content of design revisions. Reading customer code requires dedicated JTAG instructions. If the PROM is blank, or the customer code for the selected design revision was not loaded during programming, or if a specific design revision was deleted, the customer code contains all design revisions.

Additional Features of the XCFxxp Internal Oscillator The 8/16/32 MB XCFxxp Platform Flash Proms include an optional internal oscillator that can be used to drive the CLKOUT and data pins on the FPGA configuration interface. When programming the programmable ROM, the internal oscillator can be enabled and the oscillator can be set to the default frequency or a lower frequency. For internal oscillator recommendations, the "XCFxxp Decompression and Clock Options" chapter in the Platform Flash Programmable ROM User Guide.
The CLKOUT 8/16/32 MB XCFxxp platform flash prom includes programmable options to enable the CLKOUT signal, allowing the prom to provide a source synchronous clock aligned to the data on the configuration interface. The CLKOUT signal comes from one of two clock sources: the CLK input pin or the internal oscillator. The input clock source is selected during PROM programming. Output data is available on the rising edge of CLKOUT. The CLKOUT signal is enabled during programming and active when CE is low and OE/reset is high. On a CE rising edge transition, if oE/reset is high and the PROM terminal count has not been reached, CLKOUT will remain active for eight clock cycles before being disabled. CLKOUT is disabled immediately on the falling edge transition of OE/reset. When disabled, the CLKOUT pin is placed in a high impedance state and should be pulled high externally to provide a known state. When the clkout-enabled cascaded platform flash prom completes data transfer, the first prom disables clkout and drives the ceo pin to enable the next prom in the prom chain. Once the next programmable ROM is enabled and ready to transfer data, it starts driving the CLKOUT signal. In uncompressed high-speed parallel configuration, the FPGA drives the busy signal on the configuration interface. When busy is asserted high, the proms internal address counter stops incrementing and the current data value remains on the data output. When busy is high, the PROM continues to drive the CLKOUT signal to the FPGA and clock the FPGA's configuration logic. When the FPGA comes out of the busy state, indicating that it is ready to receive additional configuration data, the PROM starts driving new data onto the configuration interface.
Decompress 8/16/32 MB XCFxxp Platform Flash Proms includes a built-in data decompressor compatible with Xilinx advanced compression technology. Compressed Platform Flash PROM files are created from the target FPGA bitstream using IMPACT software. From serial number only and from serial number

FPGA configuration supports selectmap (parallel) configuration mode when using xcfxp prom programmed with compressed bitstream. Compression ratio depends on several factors, including target device family and target design content. Enable decompression option during PROM programming. The PROM decompresses the stored data before driving the clock and data to the FPGA's configuration interface. If decompression is enabled, the platform flash clock output pin (CLKOUT) must be used as the clock signal for the configuration interface, driving the configuration clock input pin (CCLK) of the target FPGA. The clock input pin of the programmable ROM or the internal oscillator must be selected as the clock output source. Any target FPGA connected to the programmable ROM must operate as a slave in the configuration chain, with the configuration mode set to either slave serial mode or slave select mapped (parallel) mode. When decompression is enabled, the CLKOUT signal becomes a controlled clock output with a reduced maximum frequency. When decompressed data is not ready, the CLKOUT pin is placed in a high-Z state and must be pulled high externally to provide a known state. When decompression is enabled, busy input is automatically disabled. For details on settings, see the "Extraction Settings" section in the platform's flash prom user guide.
Design Modifications Design Modifications allow users to create up to four unique design modifications on a single PROM, or store in multiple cascaded PROMs. The 8/16/32 MB XCFxxp platform Flash Proms support design modifications in both serial and parallel modes. Design modifications can be used with compressed PROM files or when the CLKOUT function is enabled. Programmable ROM programming files and revision information files (.cfi) are created using IMPACT software. A .cfi file is required to enable design revision programming in Impact. A single design revision consists of 1 to N 8 MB memory blocks. If a single design revision contains less than 8 MB of data, the remaining space will be filled with all data. Larger design revisions can span several 8 MB memory blocks, and all space remaining in the last 8 MB memory block will be filled. 8226 ; a single 32MB programmable read-only memory contains four 8MB memory blocks, so it can store up to four separate design revisions: one 32MB design revision, two 16MB design revisions, three 8MB design revisions, four 8MB design revisions, and many more.

Initiate FPGA configuration Options for initiating FPGA configuration through the platform flash prom include: • Auto-configuration at power-up • Apply external pulses to FPGA program _b pin • Apply jtag configuration to prom following FPGA power-up sequence or assertion of program _b pins, fp instruction. The GA's configuration memory is cleared, the configuration mode is selected, and the FPGA is ready to accept a new configuration bitstream. The program B pin of the FPGA can be controlled by an external source, or the platform flash prom includes a CF pin that can be bound to the program B pin of the FPGA. Execute the configuration command through JTAG, pulse the CF output low once for 300-500 ns, reset the FPGA and start the configuration. Affected software can initiate FPGA configuration by issuing the jtag config command with the "Load FPGA" option set.
When using the XCFxxp Platform Flash Programmable ROM with design modifications enabled, the CF pins should always be connected to the program pins on the FPGA to ensure that the current design modification selection is sampled when the FPGA is reset. The xcfxxp prom samples the current design revision selection from external rev_sel pins or an internal programmable revision selection bit on the rising edge of CF. When the jtag config command is executed, xcfxxp samples the new design revision selection before initiating the FPGA configuration sequence. When using the XCFxp Platform Flash PROM without modifying the design, the XCFxp CF pins must be tied high if the CF pins are not connected to the B pins of the FPGA program.

Power-on reset and power-on reset are active, and the device requires the VCCINT supply to rise monotonically to the rated operating voltage within the specified VCCINT rise time. If the power supply does not meet this requirement, the device may not perform a power-on reset properly. During power-up, the programmable ROM holds OE/reset low. Once the required power supplies reach their respective POR (Power-On Reset) thresholds, the OE/reset release is delayed (to the minimum) to allow the power supplies to stabilize before starting the configuration. The OE/reset pin is connected to an external 4.7 kΩ pull-up resistor and also to the initial pin of the target FPGA. For systems using slow power supplies, additional power supply monitoring circuitry can be used to delay target configuration until the system power supply has passed by holding the oE/reset pin low to the minimum operating voltage. When oe/reset is released, the fpga's init pin is pulled high, allowing the fpga's configuration sequence to begin. If the power drops below the power-down threshold (VCCPD), PROM reset and OE/reset are held low again until the POR threshold is reached. OE/reset polarity is not programmable. These power-up requirements are shown in Figure 6. For full power platform Flash PROM, reset occurs whenever OE/reset (low) is asserted or CE is de-asserted (high). The address counter is reset, the CEO is driven high, and the remaining outputs are placed in a high impedance state. Note: 1. The XCFxXS PROM only requires VCCINT to be above its POR threshold before releasing OE/reset. 2. The xcfxxp programmable ROM requires VCCINT to be above its POR threshold and VCCO to reach the recommended operating voltage level before releasing OE/reset.

Standby Mode: Whenever CE is de-evaluated (high), the programmable ROM enters a low-power standby mode. In standby mode, the address counter is reset, the CEO is driven to a high-impedance state, and the remaining outputs are put into a high-impedance state regardless of the state of the OE/reset input. To keep the device in low power standby mode, the JTAG pins TMS, TDI and TDO must not be pulled low and TCK must be stopped (high or low). When using the FPGA completion signal to drive the programmable ROM CE pin high to reduce backup power after configuration, an external pull-up resistor should be used. Typically 330Ω
Use pull-up resistors, but refer to the appropriate FPGA datasheet for recommended pull-up values for done pins. If the completed circuit is connected to an LED to indicate FPGA configuration is complete, and also connected to the PROM CE pin to enable low-power standby mode, an external buffer should be used to drive the LED circuit to ensure valid transitions on the PROM CE pin. If the programmable ROM does not require a low-power standby mode, the CE pin should be tied to ground.