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2022-09-23 12:47:03
YS12S10 DC-DC Converter
The YS12S10 converter should be connected to the DC power supply with low impedance. In many applications, the inductance associated with the distribution from the power supply to the input of the converter can affect the stability of the converter. It is recommended to use a decoupling capacitor as close as possible to the converter input (minimum 47µF) to ensure converter stability and reduce input ripple voltage. The converter has a 20µF (low ESR ceramic) input capacitor inside.
In typical applications, low ESR tantalum or POS capacitors are sufficient to provide adequate ripple voltage filtering at the input of the converter. However, to minimize input ripple voltage, it is recommended to use very low ESR ceramic capacitors of 47 to 100 μF at the input of the converter. They should be as close as possible to the input of the converter.
The YS12S10 is designed for stable operation with or without external capacitors. It is recommended to place low ESR ceramic capacitors as close as possible to the load (47µF minimum) for better transient performance and lower output voltage ripple.
Maintaining low resistance and low inductance printed circuit board traces is important for connecting loads to the output pins of the converter. This is to maintain good load regulation, as the converter has no sense pins to compensate for the voltage drop associated with the power distribution system on your PCB.
On/Off (Pin 1)
The on/off pin (pin 1) is used to remotely turn the power converter on or off via a system signal. There are two remote control options available, positive logic (standard option) and negative logic, both referenced to GND (pin 5)
The positive logic version turns on the converter when the ON/OFF pin is at logic high or left open, and turns it off when logic low or shorted to GND.
The negative logic version turns on the converter when the ON/OFF pin is at logic low or left open and turns off the converter when the ON/OFF pin is at logic high or connected to VIN.
Circuit configuration for on/off function.
The ON/OFF pin is internally pulled up to VIN for the positive logic version, and pulled down for the negative logic version. TTL or CMOS logic gates, open collector (open drain) transistors can be used to drive the on/off pins. When using an open collector (drain) transistor with the negative logic option, add a 75 kΩ pull-up (R*) on VIN as shown in Figure A. The device must be capable of: — 0.2 mA pull-down at low-level voltages of 0.8 V — 0.25 mA pull-down at high logic levels from 2.3 to 5 V — 0.75 mA pull-down when VIN is connected . - Remote sensing (pin 2)
The converter's remote sensing function only compensates for the voltage drop that occurs between the converter's VOUT pin (pin 4) and the load. The sense (pin 2) pin should be connected at the load or where it needs to be adjusted. There is no inductive function on the output ground return pin, where a solid ground plane should provide a low voltage drop.
overload
If remote sensing is not required, the sense pin must be connected to the VOUT pin (pin 4) to ensure that the converter will regulate at the specified output voltage. Without these connections, the converter will provide a slightly higher output voltage than specified. Since the sense wires carry minimal current, there is no need to leave large traces on the end user board. However, the sense trace should be close to the ground plane to minimize system noise and ensure optimal performance. When using the remote sensing feature, care must be taken not to exceed the maximum allowable output power capability of the converter, which is equal to the product of the rated output voltage and the allowable output current for the given conditions. When using remote sensing, the output voltage of the converter can be increased to 0.5 V above nominal to maintain the desired voltage across the load. Therefore, if necessary, the designer must reduce the maximum current (originally obtained from the derating curve) by the same percentage to ensure that the actual output power of the converter remains at or below the maximum allowable output power.
Output Voltage Programming (Pin 3)
The output voltage can be programmed from 0.7525 to 5.5 V by connecting an external resistor between the trim pin (pin 3) and the GND pin (pin 5); note that when the trim resistor is not connected, the output voltage of the converter is 0.7525 V. The trim resistor Rtrim for the desired output voltage can be calculated using the following formula:
Output voltage programming configuration.
Note that the tolerance of the trimmer resistor directly affects the output voltage tolerance. Standard 1% or 0.5% resistors are recommended; for tighter tolerances, two resistors in parallel are recommended instead of one of the standard values in Table 1. The ground pin of the trimmer resistor should be connected directly to the ground pin of the converter (pin 5) with no voltage drop between the two. Table 1 provides trimmer resistor values for common output voltages.
Input Undervoltage Lockout Input undervoltage lockout is standard on this converter. When the input voltage falls below a predetermined voltage, the converter will shut down; when VIN returns to the specified range, the converter will automatically start. The input voltage must typically be 9.0 V for the converter to turn on. Once the converter is turned on, it will turn off when the input voltage drops below 8.5 V.
Output Over Current Protection (OCP)
The converter has overcurrent and short circuit protection. Once an overcurrent condition is detected, the converter will enter hiccup mode. Once the overload or short-circuit condition is removed, VOUT will return to its rated value.
YS12S10 DC-DC Converter Over Temperature Protection (OTP)
The converter will shut down in overtemperature conditions to protect itself from overheating caused by operation outside the thermal derating curve or abnormal conditions such as system fan failure. After the drive has cooled to a safe operating temperature, it will restart automatically.
Safety Requirements According to UL60950 and EN60950, the converter complies with North American and international safety regulations. Under all operating conditions, the maximum DC voltage between any two pins is VIN. Therefore, the device has an ELV (Extra Low Voltage) output, meeting SELV requirements with all input voltages being ELV. The converter has no internal fuse. To comply with safety agency requirements, a recognized fuse with a maximum current rating of 15 amps must be used in series with the input line.
GENERAL INFORMATION The converter features a number of operational features, including thermal derating for vertical and horizontal mounting (maximum load current is a function of ambient temperature and airflow), efficiency, start-up and shutdown parameters, output ripple and noise, response to load step transient response to sudden changes, overloads and short circuits. The numbers are numbered as shown in figure XY, where X represents different output voltages and Y represents a specific figure (Y=1 for vertical thermal derating, …). Vertical thermal derating of all output voltages will be involved. The following pages contain specific plots or waveforms associated with the converter. Additional notes on specific data are provided below.
All data provided for the test conditions was performed with converters soldered on a test board, specifically a 0.060" thick four-layer printed wiring board (PWB). The top and bottom layers were not metallized. The two inner layers consisted of two copper, Used to provide traces to connect to the converter. No metallization on the outer layers and limited thermal connection ensures that heat transfer from the converter to the PWB is minimized. This provides a worst-case but consistent solution for thermal derating. All required Airflow measurements were made in both vertical and horizontal wind tunnels, using infrared (IR) thermal imaging cameras and thermocouples for temperature measurements. It is important to ensure that components on the converter do not exceed their ratings to maintain high reliability. If If you expect to operate the converter at or near the maximum load specified in the derating curve, you should carefully check the actual operating temperature in the application. Thermal imaging is best; if this capability is not available, a thermocouple can be used. Recommended Use AWG 40 gauge thermocouples to ensure measurement accuracy. Careful routing of thermocouple leads will further reduce measurement errors. Optimal measurement thermocouple location
The relationship between load current and ambient temperature and airflow velocity is shown in the figure. X.1 to X.2, maximum temperature 110°C. Ambient temperature varies from 25°C to 85°C, airflow velocities from 30 to 500 LFM (0.15 m/s to 2.5 m/s), vertical and horizontal converter mounting. The airflow during the test was parallel to the long axis of the converter, from pins 1 and 6 to pins 2–5.
For each set of conditions, the maximum load current is defined as the lowest of: (i) the output current at which any MOSFET temperature does not exceed the maximum specified temperature (110°C) shown in the thermal image, or (ii) the converter's maximum rated Current (10 A).
During normal operation, the derating curve for a maximum FET temperature of less than or equal to 110°C should not be exceeded. To operate within the derating curve, the printed circuit board temperature at the thermocouple location shown in Figure D should not exceed 110°C.
Efficiency shows a plot of efficiency versus load current at 25°C ambient temperature, 200 LFM (1 m/s) airflow rate, and input voltages of 9.6 V, 12 V, and 14 V.
Power dissipation shows a plot of power dissipation versus load current at Ta = 25°C, airflow velocity of 200 LFM (1 m/s), vertical mounting and input voltages of 9.6 V, 12 V, and 14 V.
Ripple and Noise The output voltage ripple waveform is measured at full rated load current. Note that all output voltage waveforms are measured with 1µF ceramic capacitors. The output voltage ripple and input reflected ripple current waveforms were obtained with the test setup shown in Figure E.