The device structure bus interface module is located between the external bus pins and the on-chip 16-bit data bus interconnected with other functional modules. It includes several flexible bus interface options controlled by the Bus Configuration Register (BCR). After reset, the BCR is automatically the target of the first write cycle from the host processor to the USC. After that, the host software can no longer access it.
Transmit Data Path Either the host processor or an external DMA channel can write transmit data to the channel's transmit first-in-first-out (FIFO) memory. At any time, the transmit FIFO can be empty or contain between 1 and 32 characters to transmit. Characters written to the txfifo are available to the transmitter in the order in which they were written.
While the host processor itself can write data to the transmit FIFOS, it is more efficient to use an external transmit DMA channel to get the data. The host can program the USC channel so that its transmitter triggers its DMA controller to fill its FIFO with varying degrees of FIFO "empty" state. Choosing this involves balancing the probability and consequences of "underrunning" the transmitter with the overhead of acquiring the DMA channel controlled by the host bus more frequently.
The serial transmitter extracts characters from the transmit FIFO and converts them to serial data on the TXD pin. Although this feature is conceptually simple, the USC supports many complex serial protocols, which greatly increases the complexity of the transmitter. Depending on the selected serial mode, in addition to parallel-to-serial conversion, the transmitter can perform any of the following operations: start, stop, and parity generation, calculate and transmit CRC, automatically generate on and off flags, convert serial Data is encoded in any of several formats to guarantee conversion and carry the clock WI. Data and/or control transfers based on the CTS pin.
Receive Data Path In general, receivers function inversely to transmitters: they monitor serial data on the RxD pins, organize it according to the serial mode selected by software, and convert the data to be placed in the receive FIFO Parallel characters in . Again, there are more processes than just serial-to-parallel conversion. Depending on the serial mode, the receiver may have to detect and synchronize start bits, check parity and stop bits, calculate and check CRC, detect flags, abort and idle sequences, recognize control characters (including transparency considerations), use several Either of the encoding schemes decodes serial data and clock extraction, and/or enables and disables reception based on the DCD input pin. . The receiver's check function generates several status bits associated with each character that accompany the character through the receive FIFO.

The receive FIFO can hold up to 32 characters and their associated status bits. When the receiver writes entries to the FIFO, those entries are available to the host processor or to an external receive DMA channel. Like the transmit side, the receive FIFO includes varying degrees of "fullness" of detection logic. A separate threshold controls the point at which a channel begins to request its DMA channel to start refilling the FIFO, and the point at which the channel requests an interruption. In addition to the main receive FIFO, each channel has a 4 RCC FIFO, which can hold values indicating the length of up to 4 received frames.
While the host processor can access data from the receive FIFO, it is more efficient to use an external receive DMA channel to transfer data directly to a buffer in memory. USC can provide the status of each frame in the serial data stream (and optionally the end RCC value) after the last character of the frame.
Clock Each channel includes a serial clock logic section that creates the clock signal for the channel's transmitter and receiver. Software can program the clock logic based on one or two external clocks per channel to do this in various ways. Each channel also includes a digital phase-locked loop (DPLL) circuit that recovers the clock from the encoded data on the RxD.
Interrupts There is also an interrupt control section in each channel, which collects various "request" lines from the transmitter and receiver, and is responsible for requesting host interrupts and responding to host interrupt acknowledgement cycles or software equivalent cycles. Interrupt operation depends on the data written to the bus configuration register and several registers in the receiver and transmitter. Each channel has a separate set of interrupt pins so that external logic can control their relative priority.

bus interface
USC can be used in systems with various microprocessors or backplane buses. Its flexibility in host bus interface comes from its bus configuration register (BCR), from the activity of the chip logic monitoring the bus before software writes to the BCR, and from certain other registers in the serial channel. This section describes how to use these facilities to interface the USC with various host microprocessors and buses.

Multiplexed/Non-Multiplexed Operation (continued)

User-friendly non-multiplexed bus interface 80x86 based systems differ in that the processor's ALE signal must be inverted to generate /AS for USC.
Two ways to connect the USC to a non-multiplexed host bus. Includes minimal hardware, but requires software to write the register address to USC each time the register is accessed. In this mode, the USC/AS pin should be pulled up to ensure a constant high logic level. Includes the driver to sort the low-order bits of the host address into the USC's AD row, and the logic to synthesize pulses on the /AS pin. The advantage of this interface method is that software can directly address the registers of the USC.

From the /reset pin going high until software writes to the bus configuration register, the USC monitors the /AS pin. If seen/displayed low at any point during this time, USC will capture the low-order AD line, A//B, C//D on every rising edge of/displayed after software has written the BCR and /C status. If /as is held high, software may have to write each register address to the Channel Command/Address Register (CCAR) before reading or writing the register. (If the host bus consists of only 8 data lines, the AD13-AD8 can carry register addresses.)

Another difference between read/write data strobes on the host bus is how read and write cycles are signaled and differentiated. Two standard methods supported by USC. The bus includes separate strobe lines for read and write cycles, commonly referred to as /rd and /wr. The bus includes a data strobe line /ds (both read and write cycles go low), and an r/w line (to differentiate between read and write cycles). USC includes pins for all four signals. Two signals matching the host bus signals should be connected to these signals. The two unused pins should be pulled to a higher level.

There are no programmable options to differentiate between /rd-/wr and r//w-/ds operations. USC only responds to any pair of wires, which is why it's important to unplug unused pairs. Also, USC does not require the R//W line to remain active during the /DS assertion. It captures the state of r//w on the leading/trailing edge of /ds, so r//w only needs to satisfy the setup and hold times associated with that edge.
Only one of the bus signals /ds, /rd, /wr, and /pitack can be active at a time. This disable also includes /rxacka, /rxackb, /txacka, and /txackb when these pins are used as DMA acknowledge signals. (The DMA interface that includes the "ACK" signal will go into an inactive state if the USC detects that more than one input is active at the same time, the only escape is via the /reset pins.

Another major difference between bus width host buses is the number of data bits that can be transferred in one cycle. Software can configure USC to transfer 16 bits at a time, in which case 8 bits can still be transferred when needed or desired. Alternatively, software can limit the operation to transfer only 8 bits at a time on the AD7-AD0 pins.
This leaves the AD15-AD8 pins unused: another BCR option allows them to carry register addresses. The latter option allows software to address the USC register directly, even on a non-multiplexed bus, without having to write the address to the USC before accessing the register.

The last major difference between the ACK and WAIT handshake master bus is the nature of the handshake signal, which is used by the slave device for speed matching with the master device. Figures 2-6 illustrate three commonly used variants. First, we call it a wait signal, if the master selects the slave, and the slave cannot capture write data or provide read data in the time allowed, leaving the master running at full speed, it drives fast (combinatorially) Wait for the output to be low, then return high when ready to complete the loop. Some peripherals have OpenCollector or open-drain wait outputs that can be wired together for a negative logic wired-OR function. Since the USC drives its /wait//rdy output high or low in a full-time fashion, the logic gate must be used for negative logic OR (positive logical sum) of its /wait//rdy output with the /wait signal from other slaves, to generate /wait input to a host device such as a processor.
In the second scheme, "acknowledgment" signaling, when the master sends a cycle to all slaves, all slaves must respond, by lowering the acknowledgment signal (sometimes called /dtack) to allow the master to complete the transmission, and keep the signal low until the master completes the transfer. As with the previous scheme, some peripherals provide slave ACK outputs, which are open collectors or open drains that can be wired together for negative logic wired-OR functions. Since the USC drives its /wait//rdy output high or low in a full-time fashion, logic gates must be used for negative logic or its /wait//rdy output with the /ack signal from other slaves to generate a response to the master confirmation input.
In the third scheme, the "ready" signal, when the master sends a cycle to all slaves, all slaves must respond by driving the ready signal high to allow the master to complete the transfer, and hold the high position until the master device completes the transfer. This scheme differs from the wait signal (wait signal high, ready signal low) in the default state of the handshake signal between cycles. It has similar timing to the ACK signal, but the polarity of the handshake signal is different. With ready signaling, the board designer must include a logic gate to positive logic or ready lines from various slave devices to produce a composite ready input for the bus master.
USC supports acknowledgment and ready signals for all cycles, and waits for signals that interrupt the acknowledgment cycle. The access time of the USC register should be short enough to avoid all but the fastest processors needing to wait for a signal. Board Designer can combine the USC's /wait//rdy output with similar signals from other slaves via an external logic gate or (for acknowledge and wait) an external tri-state or open collector driver.
If software writes the Bus Configuration Register (BCR) to an address that makes the A//B pin low, the USC drives /wait//rdy low as an "acknowledge" signal, while if software writes the BCR to A//B high, Then the USC drive /wait//rdy acts as a "wait" signal.

Pin description reset. reset(input, active low). A low on this line places the USC in a known inactive state and conditions it so that data from the next assertion/write operation of the cs pin goes into the bus configuration register (BCR) without Consider register addresses. / Reset should be lowered as soon as possible during power-up and as needed when the entire system or communications subsystem is restarted.
AD15 AD0. Address/Data bus (input/tri-state output). These lines carry data between the controlling microprocessor and the USC, as well as multiplexed addresses for registers within the USC. These lines also transfer data between the USC and system memory or the DMA controller if the USC is used with an external DMA controller. The AD15-AD0 can be used in a number of ways depending on whether the USC senses active on/off after reset and data written to the Bus Configuration Register (BCR).
/CS. Chip select (input, active low). A low value on this line indicates that the current bus cycle controlling the microprocessor refers to a register in the USC. USC ignores /CS when LOW ON/SITACK or /PITACK indicates that the current bus operation is an interrupt acknowledgement cycle. On a multiplexed bus, usc latches the pin's state on a rising edge on /as, while on a non-multiplexed bus, it's on a rising/falling edge on /ds, /rd, or /wr lock/cs.
A//B. Channel selection (input, high means "Channel A"). Cycle the high access register of channel A with /cs low and /sitack, /pitack and this pin. Cycle the low access register of channel B with /sitack and /pitack high and /cs together with this pin to cycle the low access register of channel B. The state of this line when writing to the bus configuration register determines "waiting"
and confirm operations, as described later in this chapter. On a multiplexed bus, usc latches the pin's state on a rising edge on /as, while on a non-multiplexed bus, it's on a rising/falling edge on /ds, /rd, or /wr Lock this state.
D//C. data/control (input, high for data). A read loop with /cs low and /sitack, /pitack and this pin high fetches data from the receive FIFO of the channel selected by A//B through its receive data register (RDR). A write cycle with the same conditions writes data to the transmit FIFO for that channel through its transmit data register (TDR). A loop to read or write the USC register using /sitack and /pitack high and /cs and this pin low. On a multiplexed bus, the USC determines which register is accessed from the low-order AD line on the rising edge of /AS. On non-multiplexed buses, it usually selects the register based on the LSBits of the serial controller channel command/address register. On a multiplexed bus, usc latches the pin's state on a rising edge on /as, while on a non-multiplexed bus, it's on a rising/falling edge on /ds, /rd, or /wr Lock this state.
. Address strobe (input, active low). After reset, the USC's bus interface logic monitors this signal to see if the host bus is multiplexing address and data on AD15-AD0. If the logic sees activity before (or as) software writes to the bus configuration registers, then in the subsequent loop to USC, it captures register selects from AD row, A//B and D//C (located in /as rising edge).
For non-multiplexed buses, this pin should be pulled up to +5 V. If the processor uses a non-multiplexed bus, but the output is named address strobe (like a 680X0 device), this pin should not be connected to the output.

Pin Description (Continued)
Read/write control (input, low for "write"). r//w and /ds represent read and write cycles on the bus for host processors/buses with such signals. usc samples r//w at every leading/trailing edge on /ds.
/DS. Data Strobe (input, active low). r//w and /ds represent read and write cycles on the bus for host processors/buses with such signals. It is qualified by /cs low or /sitack low. USC samples r//w at every leading/trailing edge on this line. For a write cycle, the USC captures data on the rising (trailing) edge of the row. During a read cycle, the USC provides valid data on the AD line for the specified access time after the line goes low, and the data remains valid until the master goes high on the line.
/read strobe light (input, active low). This row represents a read cycle on the bus for the host processor/bus with this signal. It is qualified by /cs low or /sitack low. During a read cycle, the USC provides valid data on the AD line for the specified access time after the line goes low, and the data remains valid until the master drives the line back high.
/WR. Write strobe (input, active low). This row represents a write cycle on the bus for the host processor/bus with this signal. It is qualified by /cs low. USC captures the write data on the rising (trailing edge) of the row.
Only one of /ds, /rd, /wr, or /pitack can be driven low during each bus cycle. This limit also includes /txack and/or /rxack (if they are used as "flyby" DMA acknowledgement signals).
wait. Wait, prepare or confirm handshake (output, active low). This row can carry a "wait" or "acknowledge" signal, depending on the state of the A//B input during the initial BCR write. If a//b is high when the BCR is written, this line runs thereafter as a ready/wait line for Zilog and some Intel processors. In this mode, the USC asserts the line low until it is ready to complete the interrupt acknowledgement loop, but it never asserts the line when the host accesses one of the USC registers.
If A//B is low when the BCR is written, the line then runs as a confirmation line for Motorola and some Intel processors. In this mode, USC asserts this behavior low for register read and write cycles and when ready to complete an interrupt acknowledge cycle.
In any case, this is a full-time output. Board Designer can combine this signal with similar signals from other slave systems through external logic gates or tri-state or open collector drivers.

/INTA, B. Interrupt request (output, active low). When (1) its IEI pin is high, (2) one or more of its interrupt types are enabled and pending, and (3) the service interrupt flag is not set to its highest priority enabled/suspended type, or within a channel When any high-priority type, the channel drives its /int pin low. USC always drives these pins high or low - they are neither tri-stated nor open-drain pins.
/sitting, /sitting. Interrupt acknowledgement (input, active low). A low value on one of the lines indicates that the host processor is executing an interrupt acknowledgement cycle. In some systems, a low value on one of the lines may further indicate that external logic has selected this USC as a device to acknowledge, or as a potential device to acknowledge. The two signals differ in that /sitack should be used for level-sensitive "status" signals, USC should be sampled on the leading edge of /as or /ds, and /pitack should be used for single-pulse or double-pulse protocols. The other unused pin should be pulled to a higher level. The channel will respond to the interrupt acknowledgement loop in various ways depending on its /int and iei lines, as described in Chapter 7.
IEIA, B. Interrupt Enable Input (input, active high). These signals and IEO pins can be part of an interrupt acknowledgement daisy chain for use with other devices that may request interrupts. If a channel's IEI pin is high outside of an interrupt acknowledgement period, and one or more interrupt types for that channel are enabled and pending, and the interrupt under the service flag is not set to the (highest priority such) type, Nor is it set to any higher priority type within the channel, then the channel requests an interrupt by driving it. S/INT pin low. If a channel's IEI pin is high during an IACK cycle, then one or more interrupt types in that channel are enabled and pending, and the "Service Interrupt" flag is not set to the (highest priority such) type or in the channel of any higher priority type, the channel forces its IEO line low and responds to the cycle.
Interrupt enable output (output, active high). These signals and IEI pins can be part of an interrupt acknowledgement daisy chain for use with other devices that may request interrupts. A channel drives its IEO pin low whenever its IEI pin is low, and/or whenever an interrupt under a service flag is set for any type of interrupt within the channel. During the interrupt acknowledgement cycle, these signals operate slightly differently because if a channel is (already) requesting an interrupt, it also forces its IEO pin low.
VCC, VSS. power and ground. Each power rail contains seven pins, ensuring good signal integrity, preventing output transients, and improving input noise margin. USC's internal power distribution network requires all of these pins to be properly connected.

Pull-Up Resistors and Unused Pins All unused input pins should be pulled up either directly to VCC or with a resistor. This may include /pitack, /sitack, iei, and /abort.
Bidirectional pins should usually be pulled up with a resistor of about 10kohms to allow the USC to drive them as an output. This may include /txreq, /rxreq, /txc, /rxc, /cts, and /dcd.
Tri-state output pins may need to be pulled up to protect external logic from floating inputs. Again, a resistor of about 10k ohms is recommended. This may include /txreq, /rxreq, txd, and /int.

Bus Configuration Register (BCR) The BCR is a 16-bit register and all bits in the BCR are reset to zero. The first software access to the USC™ after a hardware reset must be a write to the BCR. If the host processor handles 16-bit data, and the data bus between it and the USC is at least 16 bits wide, then the initial software access to the USC should be a 16-bit write. This write can be to the address of any active/cs pin; the data will be placed in the BCR. If the host can only write bytes to USC, all data should be transmitted on the AD7-AD0 pins. In such a system, pull-down resistors should be connected to the AD15-AD8 pins to ensure the state of these lines during BCR writes. (AD15 may need to be pulled up instead of pulled down, as described in the SEPAD bits section below.)
Wait and Ready Select When software writes to the BCR, the USC captures the state of the A//B pins. It uses this captured state after a BCR write so that if a//b is low, it drives the /wait//rdy pin as "acknowledge" (or inverted "ready") during the register access and interrupt acknowledgement loop signal, while if a//b is high, it only drives the pin as a "wait" signal during the interrupt acknowledgement loop. Therefore, software should program the BCR at an address corresponding to the type of slave-to-master handshake used on the master bus.
Bits and fields in BCR
sepad (separate address; bcr15): This bit can only be written as 1, bit 16=0. This combination enables the USC to use AD7-AD0 for data processing and to obtain register addresses from AD13-AD8. In this mode, the USC receives up/down byte indication (U//L) from AD8 and register addresses from AD13-AD9.
Using this interface technique, BCR must be written at an address so that AD13-AD8 are low/zero. Also, when software writes to the BCR, AD15 must be high/one and AD14 must be low/zero. Designers can ensure this by connecting AD15 and AD14 to more significant address lines and writing the BCR at the appropriate address. Alternatively, the designer can ensure this by connecting a pull-up resistor to AD15 and a pull-down resistor to AD14.
This mode is useful for non-multiplexed buses to avoid having software write register addresses to CCAR before each register access. In this mode, USC captures the AD13-AD8 state of each leading/trailing edge on /ds, /rd, or /wr. However, software can still program SEPAD=1 (16bit=0) when USC detects early activity on /AS. In this case, the USC captures the address from AD13-AD8 on every rising edge of /AS, not from the lower-order AD row as it does when SEPAD=0.

Bits and Fields in BCR (continued)
16-bit (BCR2): This bit should be written as 1 when the host data bus is 16 bits wide (or wider). Writing this bit to 0 has two effects: it restricts the host to use byte transfers on AD7-AD0 when reading and writing USC registers, and causes the USC to ignore the "b//w" signal or the state of the register access bits. This bit also controls whether "implicit" accesses to CCAR, TDR, and RDR are 8-bit or 16-bit wide.
2pulseiack (double pulse interrupt acknowledge; bcr1): If the /pitack pin is not used, or if it carries a single pulse when the interrupt is acknowledged by the host processor, software should program this bit to 0; if the /pitack is interrupted by the host processor acknowledgement When carrying two pulses, software should program it to 1. (The latter mode is compatible with some Intel processors.)
srighta (shift right address; bcr0): This bit is only valid for multiplexed buses - for non-multiplexed buses, the USC ignores this bit. If srighta is 1, the USC captures the register address from the AD6-AD0 pins and ignores the AD7 pin. In this mode, AD0 carries the upper/lower byte indication (U//L), AD5-AD1 carry the actual register address, and AD6 carries the byte/word indication (B//W). If srighta is 0, the USC captures the address from AD7AD1 and ignores AD0. It takes u//l from AD1, register addresses from AD6-AD2, and b//w from AD7. This bit has no effect on the use of the S//D and D//C pins.
When using USC as an 8-bit peripheral on a 16-bit bus, the srighta will be 0, which is unlikely to be a common application. Some sections of this manual assume srighta is 1.
All other bits in BCR are reserved and should be programmed to 0. If the processor can only write bytes to the USC, software can only write the 8 LSbits of the BCR on lines AD7-AD0. In this case, when software writes to the BCR, the state of the AD15-AD8 must be ensured by connecting these pins to pull-down resistors or (if SEPAD=1) to the host address line.

Register Addressing The flowchart in Figure 2-9 shows how the USC determines which register to access when the host processor cycle asserts one of /cs and /rd, /wr, or /ds.
In all register accesses, the A//B pins select between two serial channels in the USC. USC Sample A//B and other pins described below, on the rising/trailing edge of /AS, or on the falling edge of /DS, /RD, or /WR if /AS is pulled up so that it is always high /leading edge.
Implicit Data Register Addressing If the USC samples the D//C pin high, a write operation accesses the transmit data register (TDR) and a read operation selects the receive data register (RDR). If bit 16 in the bus configuration register (BCR2) is 1 (representing a 16-bit data bus), the access is implicitly 16-bit wide; if BCR2 is 0, the access is implicitly 8-bit wide.
This means that on a 16-bit bus, software can neither write a byte to the TDR/TXFIFO nor read a byte from the RDR/RXFIFO using an address that makes D//C high. Instead, software must provide the explicit address of the ls byte of the TDR/RDR directly, or write it to the CCAR.
Direct Register Addressing on AD13-AD8 If the USC sample count D//C is low and the SEPAD bit in the bus configuration register (BCR15) is 1 (for 8-bit data bus only), the USC samples the AD13-AD9 pins as REGAD to select the register to access, sample AD8 as U//L to select the register byte to access. USC always interprets a U/L bit as "little endian", with 1 representing the more significant 8 bits in the register.
If, in this mode, the USC samples AD13-AD8 to all zeros, indicating the Channel Command/Address Register (CCAR), the USC uses the contents of the CCAR to select which register to access, as described in Indirect Register Addressing below.

Whenever a CCAR is used as an indirect address, the USC then clears CCAR6-0 to zero so that all 16 bits of the CCAR itself are referenced again the next time the CCAR address is accessed. Thus, after writing a register address to CCASS, a read or write to the CCASS address will access the register selected by the address written, but then another write to the CCASS address will reset the address again Write to CCASS.
CCAR can always be used to select a register for subsequent access to the CCAR address, even if USC detects active on/off after reset and does not take into account the state of SEPAD (BCR15).
Typically, when software uses indirect register addressing, the CCAR address is the only address it reads and writes from, all other accesses are write register addresses. Note that the CCAR itself can be accessed in a single read and write operation: for example, when writing a command to the rtcmd field on a 16-bit bus, software does not have to write the address (zero) of the CCAR first. By issuing a command in rtcmd and/or changing the rtmode field, the register address can be specified for the next access to the ccar in the same write operation.
"RxD and TXD Pins" in Chapter 4 describes how the RTMODE field in CCAR controls echo and looping between the transmitter and receiver. Typically, this field is zero, but in applications using indirect register addressing and a non-zero RTMODE value, care must be taken to preserve the current value of RTMODE when software writes the register address to the CCAR.
When indirect addressing is used, some hardware/software mechanism must prevent USC interrupts, or any interrupts that cause a context switch from the interrupted USC task, from the time the address is written to the CCAR to the time a subsequent read or write completes. This is because the address that has been written to the CCAR is part of the context of the interrupted task and wants to be saved, but such an address cannot be read from USC - reading the CCAR will return the contents of the address register.
Direct Register Addressing on AD6-AD0/AD7-AD1 If USC samples D//C low, SEPAD (BCR15) is 0, and USC detects activity before BCR or when writing to BCR, USC responds to low-order AD transistors pin sampling to determine which register to access. If srighta(bcr0) is 1, get the register selection (regad) from ad5-1; if srighta is 0, get the register selection (regad) from ad6-ad2. If bit 16 (bcr2) is 1, usc samples ad6 (or ad7 if srighta/bcr0 is 0) to b//w to determine if register (if b//w is 0) or just 8, is to access all 16 bits. If 16 bits are 0 or b//w is 1, sample ad0 (or ad1 if srighta is 0) as u//l to select which byte of the register to access. USC always interprets a U/L bit as "little endian", with 1 representing the more significant 8 bits in the register. u//l should be 0 for all 16-bit accesses.
If in this mode, the USC samples AD6-0 (or 7-1, if srighta is 1) to all zeros, indicating the channel command/address register (CCAR), the USC uses the contents of the CCAR to select the register to be accessed, as follows section described.
Indirect Register Addressing in CCAR If USC samples D/C low and:
1. SEPAD (BCR15) is 1 and USC samples AD13-AD8 are all zero, indicating CCAR, or
2. SEPAD is 0, USC detects activity before or when BCR is written, and samples AD6-AD0 to 0, indicating CCAR, or three. SEPAD is 0 and USC has not detected activity before or when the BCR was written,
It then uses the low significant byte of the CCAR to select the register to access.
Figures 2-8 show the combined capital analysis and review. The REGAD field (CCAR5-1) selects the register to be accessed when the USC takes the indirect register address from it. If 16 bits (bcr2) are 1, USC uses ccar6 as b//w to decide whether to access all 16 bits of the register (if b//w is 0) or only 8 bits. If 16 bits are 0 or b//w is 1, use ccar0 as u//l to select which byte of the register to access.
USC always interprets a u/l bit in a "little endian" way, with 1 representing the more significant 8 bits in the register. u//l should be 0 for all 16-bit accesses.

The names and addresses of addressable registers in USC. The table assumes that srighta(bcr0) is 1. The regaddr column in the table reflects the status of ad5-ad1, ad13-ad9 or ccar5-1 as applicable.
If "16 bits" (bcr2) is 1, the b//w bits from ad6, ad14 or ccar6 select 16-bit transfers (if 0/low) and 8-bit transfers (if 1). If "16-bit" is 0, USC ignores AD6, AD14, or CCAR6 (if applicable). Note that the values in the "8-bit data" column of Table 2-1 and Table 2-2 include b//w bit 1 for direct and indirect addressing, which is required on a 16-bit bus. These address values can be used as shown when 16 bits (bcr2) are 0, or 64 bits lower than the addresses shown in the "16-bit data" column.
For 8-bit transfers on an 8-bit or 16-bit bus, the state of AD0, AD8, or CCAR0 selects the least significant 8 bits (if 0/low) or the most significant 8 bits (if 1/high) of the register. In this respect, USC is "little endian" like Intel's microprocessors. For 16-bit transfers, AD0, AD8 or CCAR0 must be 0/low.

The direct address column of the table assumes: (1) srighta(bcr0) is 1,
(2) The processor's multiplex AD6-AD0 line is connected to AD6-AD0, or its A5-A0 line is connected to AD13-AD8, depending on the SEPAD (BCR15).
(3) The DC pin is grounded, and (4) the A7 wire of the processor is connected to A//B.
If your design deviates from these assumptions, register addressing will differ from what is shown in the direct address column.

Serial Data Registers TDR and RDR
RDR and TDR are actually "read and write sides of the same register location". USC ignores the state of AD4, AD12, or CCAR4 (as applicable) when the rest of the address indicates that the TDR or RDR can be accessed. For simplicity, Tables 2-1 and 2-2 show the RDR for lower addresses and the TDR for higher addresses.
MSBytes of RDR and TDR should not be read or written separately, only as part of a 16-bit access. On a Zilog 16c0x or Motorola 680x0 system, channel B uses direct address 97 or 113 (61 or 71 hex), channel A uses 225 or 241 (e1 or f1 hex), select lsbyte for byte transfers. On Intel-based systems, use address 96, 112, 224, or 240 (60, 70, e0, f0 hex) accordingly to select the lsbyte for byte transfers.
Microprocessors that differ in endianness differ in the correspondence between byte addresses and how the bytes are arranged within a 16-bit or 32-bit value. ZilogZ80 and most Intel processors use what is sometimes called a "little endian" convention: the least significant byte of a word has the smallest address, and the most significant byte has the largest address.
Zilog16c0x and Motorola680x0 processors are "bigendian": they store and fetch msbytes in low address bytes and lsbytes in high address bytes.
Addressing of bytes in USC registers is essentially "little endian", such that the largest byte of the register has an odd address.
For 16-bit serial data transfers only, two commands in the rtcmd field of the Channel Command/Address Registers (CCAR15-11) allow the USC to be used with any type of processor. The "select d15-8 first" and "select d7-0 first" commands control endianness in 16-bit transfers of serial data and should be used for DMA and processor access to RDR and TDR.
Register Read and Write Cycle The waveform of the signals involved when the host processor reads or writes the USC register. Separate drawings include signals on multiple address and data buses, and buses for separate address and data lines. On the other hand, since the waveform gets boring after the first few times, something has been done to minimize the number of numbers.
By marking the gated tracks as "/ds or /rd" and "/ds or /wr", the case of separate read and write strobes is combined with direction lines and common data strobes. The direction line r//w is shown, but a comment reminds the reader that its state is independent of /rd and /wr.
The distinction between "wait" and "acknowledge" signals is handled by displaying the /wait//rdy trace as "maybe or maybe not" going low, with appropriate labels. (The USC never asserts a "wait" indication during a register access cycle.)

is a schematic diagram of a simple USC application. It includes a USC, an 80186 integrated processor, two EPROMs, two static RAMs, and three serial interfaces.
is an octal latch that captures addresses from 186 and presents the latched addresses to RAM and EPROM. EPROM is selected by the upper chip select (/ucs) output of the 186, while RAM is selected by the lower chip select (/lcs) output. USC resides in the I/O space, one channel is selected by the first of the 186' peripheral chip select outputs (PCS0) and the other channel is selected by the other (PCS1).
The 28-pin EPROM socket is set up to accept 2764, 27128, 27256, or 27512. The 32-pin RAM socket can accept 32-pin 128KX8 or 28-pin 32KX8 static RAM.
U10 74FCT240 switches signals between an active high signal on 186 and an active low signal on USC. The /txreq and /rxreq pins of USC channel A are reversed, making DMA request 0 and 1 input for the 80186' integrated DMA channel. This means that USC channel A can operate using DMA, while USC channel B must be interrupt driven or polled. Since the 186' DMA channel uses flow-through (two-cycle) operation, the channel A/Txack and /Rxack pins are free to use in the serial interface.

The USC includes several serial interface options and features that increase its usefulness in a variety of applications. It allows various clocking schemes and will serially encode and decode for NRZI and biphase formats that carry clocking information with serial data. USC also supports this on-chip decoding digital phase-locked loop circuit. Finally, it provides I/O lines that can be connected to modem control and status signals, other control and status lines related to the serial link, and even input and/or output signals not related to the serial link.

Serial Interface Pin Description
Rxda, b. Receive data (input, positive logic). Serial input for each channel.
Send data (output, positive logic). Serial output for each channel.
/RXCA, B. Receive clock (input or output). These signals can be used as clock inputs for any functional block within each channel. Alternatively, software can program a channel so that the pin is an output that contains multiple receivers or an internal clock signal, a general purpose input or output, or an interrupt input.
/TXCA, B. Transmit clock (input or output). These signals can be used as clock inputs for any functional block within each channel. Alternatively, software can program a channel so that the pin is an output containing any of several transmitter or internal clock signals, general purpose inputs or outputs, or interrupt inputs.
/RxREQA, B. Receive DMA request (input or output). These pins can carry a low active DMA request from each channel's receive FIFO. If a DMA transfer is not intended for a channel's receiver, its RxREQ pin can be used as a general-purpose input or output, or as an interrupt input.
/Send a DMA request (input or output). These pins can transmit a low active DMA request from each channel's transmit FIFO. If a DMA transfer is not used for the channel's transmitter, its TXREQ pin can be used as a general-purpose input or output, or as an interrupt input.
/rxacka, b. Receive DMA acknowledgements (input or output). If an external "flyby" DMA controller is used for receiving data on a channel, this pin carries an active low acknowledgment signal from the DMA controller. If a channel's receiver is not using DMA transfers, or if the DMA controller is using flow-through (two cycles) instead of flying, then the channel's Rxack pin can be used as a general-purpose input or output.
/Send DMA acknowledgement (input or output). If an external "flyby" DMA controller is used to transfer data for a channel, then this pin carries a low-active acknowledgment signal from the DMA controller. If a channel's receiver is not using DMA transfers, or if the DMA controller is using flow-through (two cycles) instead of flyby operation, the txack pin for that channel can be used as a general-purpose input or output.
/Data carrier detect (input or output, active low). Software can program a channel to enable/disable its receiver for that signal. Additionally, or conversely, software can program a channel to request an interrupt in response to a transition on this line. These pins can also be used as simple inputs or outputs.
/CTSA, B. Clear to send (input or output, active low). Software can program the channel to enable/disable its transmitter for this signal. Additionally, or conversely, software can program a channel to request an interrupt in response to a transition on this line. These pins can also be used as simple inputs or outputs.