The ADS1240 and ADS1241 feature precision, wide dynamic range, delta-sigma, analog-to-digital (A/D) converters with 24-bit resolution that operate from 2.7V to 5.25V. The delta-sigma A/D converter provides up to 24 bits of no missing code performance with an effective resolution of 21 bits. Input channels are multiplexed. Internal buffering can optionally provide very high input impedance sensors or low level voltage signals for direct connection. A burnout current source is provided to allow detection of open or shorted sensors. An 8-bit digital-to-analog converter (D/A) provides offset correction over a 50% full-scale range (FSR). Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128 , with an effective resolution of 19 bits and a gain of 128. A/D conversion is accomplished using a second-order delta-sigma modulator and a programmable finite impulse response (FIR) filter. Simultaneous 50Hz and 60Hz notch. The reference input is differential and can be used for ratio conversion. The serial interface is SPI compatible. Up to 8-bit data also provides I/O that can be used for input or output. The ADS1240 and ADS1241 are designed for high-resolution measurement applications in smart transmitters, industrial process control, application weighing scales, chromatographs and portable instrumentation design.

feature

24 codes that are not missing

Simultaneous 50Hz and 60Hz rejection (-90dB MINIMUM)

0.0015% INL

21 BITS valid solution (PGA = 1), 19 bits (PGA = 128)

PGA gain from 1 to 128

Single cycle sedimentation

Programmable data output rate

External differential reference, 0.1V to 5V

On-chip calibration

SPI 8482 ; Compatible

2.7V to 5.25V supply range

600μW power consumption

Note the eight input channels

Up to 8 data I/Os.

application

Industrial Process Control

Weight ratio

Liquid/Gas Chromatography

blood analysis

SMART TRANSMITTERS

Portable Instruments

Pin Configuration (ADS1240)

Pin Configuration (ADS1241)

The input multiplexer provides any combination of differential inputs selected on any input channel, as shown in the figure below. For example, if AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative terminal channel of the differential input. Using this approach, there can be up to eight single-ended input channels or four independent differential input channels of the ADS1241 and four single-ended input channels or two independent differential input channels of the ADS1240. Note that AINCOM can be considered an input channel.

The ADS1240 and ADS1241 feature single-cycle stabilization digital filters that provide valid data on the first conversion after new channel selection. To minimize setup errors, MUX changes are synchronized to the start of a conversion, indicated by the falling edge of DRDY. In other words, the MUX change is issued via WREG as soon as DRDY goes low to command a minimized resolution error. Increasing the time between conversions begins (DRDY goes low) and the MUX change command (tDELAY) results in the establishment of incorrect data in the conversions, as shown in the figure above.

Burnout current source Burnout current source can be used to detect sensor shorted or open circuit conditions. Setting the current source (BOCS) bits in the burnout SETUP register activates two 2µA current sources called burnout current sources. One current source is connected to the negative input of the converter and the other is connected to the positive input of the converter.

The figure below shows the case of an open sensor. This is a potential failure mode for many remotely connected sensors. The current source of the positive input acts as a pull-up, causing the positive input to go to the positive analog supply, and the negative input current source acts as a pull-down, causing the negative input to ground. So the ADS1240/41 outputs full scale.

The figure below shows a shorted sensor. Since the input is the ADS1240/41 signal shorted and the potential is the same the output is about zero. (Note the code is due to internal sequences, shorted inputs are not exactly zero resistance, low level noise and other sources of error.)

The input impedance enable of the ADS1240/41 without the buffer is about 5MΩ/PGA. For systems requiring very high input impedance, the ADS1240/41 provide chopper-stabilized differential FET input voltage buffers. When activated, the buffer boosts the ADS1240/41 input impedance by approximately 5GΩ. The input range of the buffer is approximately 50mV to AVDD - 1.5V. The linearity of the buffer will be reduced outside this range. The differential signal should be adjusted so that the two signals are evenly within the input range of the buffer. The BUFEN pin can be used or the BUFEN bit in the buffer ACR register can be enabled using BUFEN. The BUFEN pin is high and the BUFEN bit is set when the buffer is on. If the BUFEN pin is low, the buffer is disabled. If the BUFEN bit is set to zero, the buffer is also disabled.

The buffer consumes additional current when active. The current required by this buffer depends on the PGA settings. When the PGA is set to 1, the buffer uses about 50µA; when the PGA is set to 128, the buffer uses about 500µA. The PGA Programmable Gain Amplifier (PGA) can be set to gain 1, 2, 4, 8, 16, 32, 64 or 128. Using a PGA can improve the effective resolution of the A/D converter. For example, with a 5V full-scale signal with a PGA of 1, the A/D converter can step down to 1µV. The PGA is 128, and the full-scale signal is 39mV, and the A/D converter can resolve down to 75nV. The current increases when AVDDPGA is set above 4. The input to the OFFSET DACPGA can be shifted by half the full-scale input of the PGA range using the Offset DAC (ODAC) register. The ODAC register is an 8-bit value; the MSB is the flag and the seven LSBs provide the magnitude of the offset. Using an offset DAC will not degrade the performance of the A/D converter.

Calibration minimizes offset and gain errors. Both the ADS1240 and ADS1241 support self and system calibration. The self-calibration of the ADS1240 and ADS1241 corrects internal offset and gain errors and is handled by three commands: SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL command performs offset and gain calibration. SELFGCAL performs gain calibration, SELFOCAL performs offset calibration, each calibration takes two tDATA cycles to complete. During self-calibration, the ADC input is internally disconnected from the input pins. The PGA must be set to 1 before issuing a SELFCAL or SELFGCAL command. PGA is allowed on any SELFOCAL command. For example, if using PGA=64, first set PGA=1 and issue. SELFGCAL. Then set PGA=64 and issue SELFOCAL.

For reference voltages greater than (AVDD - 1.5) volts, the buffer must also be turned off during gain self-calibration to avoid exceeding the buffer input range. System calibration corrects internal and external offsets and acquires errors. When performing system calibration, the appropriate signal must be applied to the input. The system offset calibration command (SYSOCAL) requires a zero input differential signal (see Table IV, page 18). The offset is then calculated, invalidating the offset in the system. The system gain calibration command (SYSGCAL) requires a positive full-scale input signal. Then it computes a value to invalidate it getting an error in the system. Each of these calibrations requires two

completed during tDATA. It is recommended to perform system gain calibration at higher PGA for best gain calibration. Calibration should be performed after power-up, temperature changes, or PGA changes. The RANGE bit (ACR bit 2) must be zero during calibration. Calibration removes the effects of ODAC; therefore, disabling ODAC during calibration and then enabling it again is done. After the calibration is complete, the DRDY signal goes low, indicating that the calibration is complete. The first data after that should discard the calibration as it may have corrupted the calibration data remaining in the filter. The second data is always valid. External Voltage Reference The ADS1240 and ADS1241 require an external voltage reference. The selection of the voltage reference value is made through the ACR register. The external reference voltage is a differential voltage, determined by the voltage difference between the pins.

The figure below shows a typical schematic diagram of a general weighing application using the ADS1240. In this example, the internal PGA is set to 64 or 128 (depending on the maximum output voltage of the load cell) to make the load cell, a schematic of a general purpose weighing scale.

Block Diagram of High Precision Weighing Scale