The CC1020 device is a true single-chip UHF transceiver designed for very low power and very low voltage wireless applications. This circuit is primarily used for ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequencies 402 , 424, 426, 429, 433, 447, 449, 469, 868 and 915 MHz, but can be easily programmed for multi-channel operation at other frequencies 402-470 MHz and 804- 930 MHz range.

The CC1020 device is particularly suitable for narrowband systems with channel spacing of 12.5 or 25 kHz in compliance with ARIB STD-T67 and EN 300 220 standards.

The main operating parameters of the CC1020 device can be programmed via the serial bus, making the CC1020 device a very flexible and easy-to-use transceiver. In a typical system, the CC1020 device will be used with a microcontroller and a few external components

passive components.

Features

True Single-Chip UHF RF Transceiver

Frequency range 402 MHz to 470 MHz and 804 MHz to 930 MHz

High sensitivity - 12.5 kHz channel up to - 118 dBm

Programmable output power

Low current consumption - RX: 19.9 mA

Low supply voltage - 2.3 V to 3.6 V.

No external IF filter required

low-IF receiver

Requires few external components

Small Size - QFN 32 Package

Lead-free package

Digital RSSI and Carrier Sense Indicator

Data rates up to 153.6 kBaud

OOK, FSK and GFSK data modulation

Integrated Bit Synchronizer

Image Suppression Mixer

Programmable frequency and AFC make crystal temperature drift compensation possible without

TCXO

Suitable for frequency hopping systems

Suitable for system-targeted compliance to EN 300 220, FCC CFR47 Part 15, and ARIB STD-T67

Easy-to-use software for generating CC1020

Configuration Data

1.2 Application

Narrowband low power UHF wireless databand channels with transmitter and receiver spacing down to 12.5 and 25 kHz

402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-, 868-, 915-MHz ISM/SRD band system

AMR - Automatic Meter Reading

Wireless Alarm and Security System

home automation

Low Power Telemetry

Functional block diagram

pin diagram

A simplified block diagram of the CC1020 device is shown in the following figure. Only signal pins are shown. The CC1020 device features a low-IF receiver. The received RF signal is downconverted to an intermediate frequency (IF) by low noise amplifiers (LNA and LNA2) and quadrature (I and Q). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADC. Automatic gain control, fine channel filtering, demodulation and bit synchronization are performed digitally. The CC102 device outputs digital demodulated data on the DIO pin. A synchronous data clock DCLK pin can be used. RSSI is provided in digital format and can be read over the serial interface. RSSI also has a programmable carrier sense indicator. In transmit mode, the synthesized RF frequencies are fed directly to the power amplifier (PA). The RF output is frequency-shift keyed (FSK) via a digital bit stream fed to the DIO pins. Optionally, a Gaussian filter can be used to obtain Gaussian FSK (GFSK). The frequency synthesizer includes a fully on-chip LC VCO and a 90-degree phase splitter in receive mode down-converting mixers to generate the LO_I and LO_Q signals. The VCO operating frequency range is from 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and VC is the control node for the on-chip VCO. The external loop filter is located between these pins. The crystal will be connected between XOSC_Q1 and XOSC_Q2. The lock signal can be obtained from the PLL. A 4-wire SPI serial interface is used for configuration.

Configuration overview

The CC1020 device can be configured to achieve optimum performance for different applications. The following key parameters can be programmed through the programmable configuration registers:

receive and transmit mode

RF output power

Key parameters of the frequency synthesizer:

RF output frequency

FSK frequency separation

Crystal oscillator reference frequency

Power-down and power-up modes

Power-down and power-up modes

Data rate and data format (NRZ, Manchester encoding or UART interface)

Synthesizer Lock Indicator Mode

Digital RSSI and Carrier Sense

FSK, GFSK and OOK modulation

TI provides a software program SmartRF Studio (Windows interface) for users of the CC1020 device to generate all the required CC1020 configuration data parameters based on the user's various choices. These hex numbers will be the necessary inputs for the microcontroller to configure the CC1020 device. In addition, the program will provide the user with the required values for the component input/output matching circuits, PLL loop filters and LC filters. The user interface of CC1020 configuration software is shown in the figure below.

Used in a typical system, the CC1020 device will interface with a microcontroller. The microcontroller must be able to:

The CC1020 device is programmed into different modes via the 4-wire serial configuration interface (PDI) PDO, PCLK and PSEL).

Interface to bidirectional synchronous data signal interfaces (DIO and DCLK).

Optionally, the microcontroller can perform data encoding and decoding.

Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status, or other status information.

Optionally, the microcontroller can read digital RSSI values and other status information by

The microcontroller interface is shown in the figure below. The microcontroller uses 3 or 4 I/O pins to configure the interface (PDI, PDO, PCLK and PSEL) PDO should be connected to the microcontroller input. PDI, PCLK and PSEL must be microcontroller outputs. If PDI and PDO are, you can save an I/O pin connected together, the microcontroller uses a bidirectional pin. Microcontroller pins connected to PDI, PDO, and PCLK can be used for other purposes. The configuration interface is not used. PDO and PCLK are high impedance inputs inactive (active low) as long as PSEL is PDI. The PSEL has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode to prevent trickle current from flowing in the pull-up circuit. Bidirectional pins are typically used to transmit data (DIO) and receive data. DCLK provides data time should be an option, the data output in receive mode can be provided on a separate pin. Optionally, a microcontroller pin can be used to monitor the LOCK signal. This signal is logic low when the PLL is in lock state. It can also be used for carrier sense and to monitor other internal test signals.

The CC1020 device is a slave device via a simple 4-wire SPI compatible interface (PDI, PDO, PCLK and PSEL). There are 8-bit configuration registers, each of which is addressed by a 7-bit address. The read/write bit initiates a read or write operation. A fully configured device for the CC1020 needs to send 33 data frames of 16 bits each (7 address bits, R/W bits and 8 data bits). The time required for full configuration depends on the PCLK frequency. A configuration with a PCLK frequency of 10 MHz completes in less than 53 ms. Putting the device into power-down mode requires sending a frame-only, which in this case will take less than 2ms. All registers are also readable. During each write cycle, 16 bits are sent on the PDI line. The seven most significant bit frames (A6:0) of each data are the address bits. A6 is the MSB (most significant bit) of the address, and as the first bit the next bit is the R/W bit (high for writing, low for reading). Then transfer 8 data bits (D7:0). During address and data transfers, PSEL (Program Select) must be held low. See below. The programming timing is shown in the figure below, and the data on PDI is completed on the rising edge of PCLK. Data should be set on the negative edge of PCLK provided by the microcontroller. When the last bit of 8 data bits, D0, is loaded, the data word is loaded into the internal configuration register. Configuration data will be retained in the programmed power-down mode, but not when the power supply is turned off. The registers can be programmed in any order. The microcontroller can also read the configuration registers through the same configuration interface. The 7 address bits are sent first, then the R/W bit is set low to initiate a data readback. CC1020 The device then returns the data from the addressed register. The PDO is used as a data output and must be configured as an input by the microcontroller. PDO is set on the falling edge of PCLK and should be sampled on the positive edge. The read operation is shown in the figure below. PSEL must be set high between each read/write operation.