Introduction Functional Architecture Overview Packaging Marking Ordering Information Modules: Functional Description DS312 (v4.2) Input/Output Block (IOB) Overview Selectio Signaling Standard Configurable Logic Block K (CLB) Block RAM Dedicated Multiplier Digital Clock Manager (DCM) Clock Network Configuration to Power Spartan 3e FPGA Production Stepper Module 3: DC and Switching Characteristics DS312 (v4.2) DC Electrical Characteristics 8226 ; Absolute Maximum Ratings • Supply Voltage Specifications • Recommended Operating Conditions • DC Characteristics • Switching Characteristics • I/O Timing • Chip Timing • DCM Timing • Block RAM Timing • Multiplier Timing G • Configuration and JTAG Timing Module 4: Pin Description DS312 (v4.2) Pin Description • Package Overview • Pin Table

Introduction: The Spartan3e family of Field Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high-volume, cost-sensitive consumer electronics applications, offering five-member families with system gate densities ranging from 100,000 to 1.6 million. The Spartan-3e family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O and significantly reducing the cost per logic cell. New features improve system performance and reduce configuration costs. Combined with advanced 90nm process technology, these Spartan-3e FPGA enhancements deliver more functionality and bandwidth per dollar than ever before, setting a new standard for the programmable logic industry. Due to its extremely low cost, Spartan 3e FPGAs are ideal for a wide range of consumer electronics applications including broadband access, home networking, display/projection and digital TV equipment. The Spartan-3e series is a better choice for mask-programmed ASICs. FPGAs avoid the high initial costs, long development cycles, and inflexibility inherent in traditional ASICs. Additionally, the programmability of FPGAs allows design upgrades in the field without the need to replace hardware, which is not possible with ASICs.
Features • Very low cost, high performance logic solution for high volume, consumer-facing applications • Mature 90nm process technology • Multi-voltage, multi-standard Selectio interface pins • Up to 376 I/O pins or 156 differential signal pairs LVCMOS, LVTTL, HSTL and SSTL single-ended signaling standards 3.3V, 2.5V, 1.8V, 1.5V and 1.2V signaling 622 +MB/s data transfer rate per I/O • True LVDS, RSDS, Mini-LVDS, Differential HSTL/SSTL Differential I/O • Enhanced Double Data Rate (DDR) support • DDR SDRAM support up to 333 MB/s • Rich and flexible logic resources • D up to 33192 logic cells , including optional shift register or distributed RAM support • Efficient wide multiplexer, wide logic • Fast look-ahead carry logic • Enhanced 18 x 18 multiplexer and optional pipeline • IEEE 1149.1/1532 JTAG Programming/Debug Ports • Hierarchical choice of RAM memory structure • Fast block RAM up to 648 kbits • Efficient distributed RAM up to 231 kbits • Up to 8 Digital Clock Managers (DCMS) • Clock Skew Elimination (Delay Locked Loop) • Frequency Synthesis, Multiplication, Division High Resolution Phase Shifting Wide Frequency Range (5 MHz to over 300 MHz) 8 Global Clocks Plus Additional 8 Clocks Each Half Device, Plus Rich Low Skew Routing Configuration interface to industry standard PROM • Low cost, space saving SPI serial flash PROM • X8 or X8/X16 parallel or non-flash PROM • Low cost Xilinx platform flash with JTAG • Complete Xilinx ISE and Webpack software • Microblaze and Picoblaze embedded processor CORES • Fully compatible with 32/64 bit 33 MHz PCI support (some devices support 66 MHz) • Low cost QFP and BGA package options • Universal package supports easy density migration • Pb-free package option • XA automotive version

Architecture Overview The Spartan-3e family architecture consists of five basic programmable functional elements: • Configurable Logic Blocks (CLBs) containing flexible look-up tables (LUTs) for implementing logic plus use as flip-flops or latches storage element. The CLB performs various logical functions and stores data. • Input/Output Blocks (IOBs) control the flow of data between input/output pins and the device's internal logic. Each IOB supports bidirectional data flow plus 3-state operation. Multiple signaling standards are supported, including four high-performance differential standards. Includes double data rate (DDR) registers. • Block RAM provides data storage in the form of 18 kbit dual port blocks. • The multiplier block accepts two 18-bit binary numbers as input and computes the product.
• The Digital Clock Manager (DCM) module provides a self-calibrating all-digital solution for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 1. An IOB ring surrounds a regular array of CLBs. Each device has two columns of block RAM, except for the XC3S100E, which has one column. Each RAM column consists of several 18 kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMS is in the center, two are on the top of the unit, and two are on the bottom of the unit. The xc3s100e has only one DCM at the top and bottom, while the xc3s1200e and xc3s160e add two DCMs in the middle of the left and right. The Spartan-3e series has a rich tracking network that interconnects all five functional elements, in which signals are transmitted. Each functional element has an associated switch matrix, allowing multiple connections to be routed.

Configuring the spartan-3e FPGA is programmed by loading configuration data into a robust, reprogrammable static CMOS configuration latch (CCL), which collectively controls all functional elements and routing resources. The configuration data of the FPGA is stored in an external programmable read-only memory or other non-volatile medium, either on or off the board. After power up, configuration data is written to the FPGA using any of the following seven different modes: • Main serial flash prom from the xilinx platform • Serial peripheral interface (SPI) from industry standard SPI serial flash • From industry standard Byte Peripheral Interface (BPI) of X8 or X8/X16 parallel NOR flash up or down SLAve serial, usually downloaded from the processor Slave parallel, usually downloaded from the processor Boundary scan (JTAG), usually downloaded from the processor or System Tester Download. Additionally, spartan-3e FPGAs support multi-boot configuration, allowing two or more FPGA configuration bitstreams to be stored in a single parallel NOR flash. The FPGA application controls which configuration is loaded next and when.
I/O Features The Spartan-3e FPGA Selectio interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os and the number of differential I/O pairs available for each device/package combination. The Spartan-3e FPGA supports the following single-ended standards: • 3.3V Low Voltage TTL (LVTTL) • Low Voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V or 1.2V • 3V PCI at 33MHz, in some In device, 66MHz at 1.8V • HSTL I and III, typically used for memory applications • SSTL I at 1.8V and 2.5V, typically used for memory applications N-3E FPGAs support the following differential standards: • LVDS • Bus LVDS• Micro LVDS • RSDS • Differential HSTL (1.8V, Type I and III) • Differential SSTL (2.5V and 1.8V, Type I) • 2.5V LVPECL input

As described in the architecture overview, the Spartan-3e FPGA architecture consists of five basic functional elements: • Input/Output Blocks (IOBs) • Configurable Logic Blocks (CLBs) and Slice Resources • Block RAMs • Dedicated Multipliers • Digital Clocks Manager (DCMS). The following sections provide n each function. In addition, this section describes the following functions: • Clocking Infrastructure • Interconnect • Configuration • Powering the Spartan-3e FPGA
IOB Overview Input/Output Blocks (IOBs) provide a programmable, unidirectional or bidirectional interface between package pins and the internal logic of the FPGA. IOBs are similar to the Spartan-3 family with the following differences: • Only input blocks are added • Programmable input delays are added to all blocks • DDR flip-flops can share a unidirectional input block between adjacent IOBs with a subset of the full IOB functionality. Therefore, the output path has no connections or logic. The following paragraphs assume that any references to output functions do not apply to input-only blocks. Only the number of input blocks varies with device size, but never exceeds 25% of the total number of IOBs. Simplified diagram of the internal structure of the IOB. There are three main signal paths in the IOB: the output path, the input path, and the tristate path. Each path has its own pair of storage elements that can be used as registers or latches. For more information, see Stored Element Functions. The three main signal paths are as follows: • The input path transfers data directly from the pad (the pad is connected to the package pin) to the I line through an optional programmable delay element. After the delay element, by pairing the storage element to the iq1 and iq2 rows. The IOB outputs i, iq1 and iq2 lead to the internal logic of the FPGA. A delay element can be set to ensure that the hold time is zero (see Input Delay Function). • The output path starts from the O1 and O2 lines and transfers the data from the FPGA internal logic through the multiplexer and then the tri-state driver to the IOB board. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. • The 3-state path determines when the output driver is high impedance. The T1 and T2 lines pass data from the FPGA's internal logic to the output drivers through a multiplexer. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. • All signal paths into the IOB, including those associated with storage elements, have an inverter option. Any inverters placed on these paths are automatically absorbed into the IOB.

Input Delay Function Each IOB has a programmable delay block that can optionally delay the input signal, and the signal path has a coarse delay element that can be bypassed. The input signal then powers the 6-tap delay line. Coarse and tap delays vary; see timing reports for specific delay values. All six taps are available directly into the FPGA fabric as asynchronous inputs via the multiplexer. In this way, the delay can be programmed in 12 steps. Three of the six taps can also be connected to the D input of the synchronous storage element through a multiplexer. The delay inserted into the storage element path can be changed in six steps. The first coarse delay element is common to both asynchronous and synchronous paths, and the coarse delay element must be used or not used for both paths. Delay values are set once in silicon at configuration time, they are not modifiable during device operation. The main purpose of the input delay element is to adjust the input delay path to ensure that hold time is not required when using the input flip-flop with a global clock. The default value is automatically chosen by the xilinx software tool, as the value depends on the device size and the specific device edge on which the trigger is located. The values set by the xilinx ISE software are displayed in the map.
Reports generated by the implementation tool, and the impact on input timing, are reported using the Timing Analyzer tool. If the design uses DCM in the clock path, then it is safe to set the delay element to zero because delay locked loop (DLL) compensation automatically ensures that there is still no input hold time requirement. Both asynchronous and synchronous values can be modified, which is useful in situations where additional latency is required for clock or data input, for example, in interfaces to various types of RAM. These delay values are defined by the ibuf_delay_value and ifd_delay_value parameters. The default ibuf_delay_ value is 0, bypassing delayed elements of async input. User can set this parameter to 0-12. The default ifd_delay_ value is auto. For each input, ibuf_delay_value and ifd_delay_value are independent. Both parameters can be used if the same input uses both registered and unregistered input paths, but they must both be within half of the total delay (both bypass or use coarse delay elements).

Storage Element Function There are three pairs of storage elements per IOB, one pair for each of the three paths. These storage elements can be configured as edge-triggered D-type flip-flops (fd) or level-sensitive latches (ld). Pairs of storage elements on the output path or tri-state path can be used with dedicated multiplexers to produce double data rate (DDR) transfers. This is done by taking the data in sync with the rising edge of the clock signal and converting it into bits that are synchronous on the rising and falling edges. The combination of two registers and a multiplexer is called a double data rate D-type flip-flop (ODDR2). Table 4 describes the signal paths associated with storage elements.

The output shares a common clock with the upper-level registers in the three state paths. The OTCLK1 clock signal drives the output and the CK clock input of the upper-level registers on the three status paths. Likewise, otclk2 drives the output and the ck input of the lower register on the three state paths. The upper and lower registers on the input path have separate clock lines: ICLK1 and ICLK2. OCE enables the CE input of the upper and lower registers on the row control output path. Likewise, the TCE controls the CE input of the register pair on the tri-state path, while the ICE pair has the same CE input for the register pair on the input path. The set/reset (SR) line that goes into the IOB controls all six registers, as does the reverse (REV) line. In addition to the signal polarity control described in the IOB overview, each storage element supports

Double Data Rate Transfer Double Data Rate (DDR) transfer describes a technique for synchronizing a signal to the rising and falling edges of a clock signal. The spartan-3e device uses register pairs in all three IOB paths to perform DDR operations. A pair of storage elements on the IOB output path (OFF1 and OFF2) acts as a register, combined with a special multiplexer to form a DDR D-type flip-flop (ODDR2). This primitive allows DDR transfers where the output data bits are synchronized with the rising and falling edges of the clock. DDR operation requires two clock signals (usually 50% duty cycle), one is the inverted version of the other. These signals toggle the two registers in an alternating fashion, as shown in Figure 7. A digital clock manager (DCM) generates two clock signals by mirroring the input signal and then shifting it 180 degrees. This method ensures minimal deviation between the two signals. Alternatively, an inverter within the IOB can be used to invert the clock signal, thus using only one clock line and the rising and falling edges of that clock line as two clocks for the DDR flip-flop.
Pairs of storage elements on tri-state paths (tff1 and tff2) can also be combined with local multiplexers to form DDR primitives. This allows synchronous output enable to the rising and falling edges of the clock. This DDR operation is implemented in the same way as the output path. Pairs of storage elements on the input paths (iff1 and iff2) allow the I/O to receive DDR signals. The incoming DDR clock signal triggers one register, while the reverse clock signal triggers the other register. The registers take turns capturing the bits of the incoming DDR data signal. The primitive that allows this functionality is called iddr2. In addition to high bandwidth data transfer, the DDR output can be used to replicate or mirror the clock signal on the output. This method is used to transmit clock and data signals simultaneously (sync source). A similar approach is used to reproduce the clock signal at multiple outputs. The advantage of these two methods is that there is minimal deviation between the outputs.
In the spartan-3e family, one IOB in a differential pair can cascade its input storage elements with those in another IOB as part of a differential pair. This is to make DDR high-speed operation easier to achieve. The new DDR connections available are shown in Figure 5 (dashed lines) and are only available for routing between IOBs and are not accessible by the FPGA fabric. Note that this feature is only available when using the differential I/O standard lvds, rsds, and mini_lvds.

Pairs of storage elements on tri-state paths (tff1 and tff2) can also be combined with local multiplexers to form DDR primitives. This allows synchronous output enable to the rising and falling edges of the clock. This DDR operation is implemented in the same way as the output path. Pairs of storage elements on the input paths (iff1 and iff2) allow the I/O to receive DDR signals. The incoming DDR clock signal triggers one register, while the reverse clock signal triggers the other register. The registers take turns capturing the bits of the incoming DDR data signal. The primitive that allows this functionality is called iddr2. In addition to high bandwidth data transfer, the DDR output can be used to replicate or mirror the clock signal on the output. This method is used to transmit clock and data signals simultaneously (sync source). A similar approach is used to reproduce the clock signal at multiple outputs. The advantage of these two methods is that there is minimal deviation between the outputs.
IDDR2 acts as a DDR input pair, the master IOB registers input data on the rising edge of ICLK1 (=d1) and the rising edge of ICLK2 (=d2), which is usually the same as the falling edge of ICLK1. This data is then transferred into the FPGA fabric. At some point, both signals must enter the same clock domain, usually ICLK1. At high frequencies, this can be difficult because, assuming a 50% duty cycle, the available time is only half the clock period.