A maximum high -end drives can be configured

RDSON Maximum 1.5 @TJ 25 ° C

The current limit of each output is at least 0.8a

Power voltage 4.75V to 5.25V

The output voltage clamping minimum 35V (low voltage side mode)

output voltage clamp -30V (high voltage side mode)

Data General Credit SPI interface

2 additional PWM input

All output heat shutdown

Open load detection in the closing mode

Output output Reverse Battery Protection (AMB)

High -voltage side grounding configuration

Output

L9848 Integrated circuit is a one is one The highly flexible single-piece medium contains 2 special current output drives low-end output (output 7-8) and 6 can be used as an internal low-end or high-end driver arbitrary combination (output 1-6). In addition, the two outputs can be pwmed through the external pin (output 5-6). Integrated standard serial peripheral interface (SPI) controls all outputs and provides diagnostic information. Integrated clamp circuit, the waves are shaped, positive, negative voltage transient protection, the scope of heat shutdown vehicles and industrial application of all output

Absolutely maximum rated value

Voltage and current. If this part is removed from the specified absolute maximum rated range, it may cause damage that cannot be repaired

Operation conditions

If the maximum rated value exceeds the maximum rated value This part may not work. Once the condition is restored to

, the maximum rated or power specified by the

is re -loop, and the parts will be restored without damage or degeneration.

Electricity

DC features , Vbatt 9V to 18V, unless there are other regulations)

Electric characteristics (continued)

DC characteristics

(tj - 40 ° C to 150 ° C, VDD 4.75VDC to 5.25VDC, VBATT 9V to 18V, unless there are other regulations)

communication characteristics

(TJ -40 ° C to 150 ° C, VDD 4.75V to 5.25VDC, VBATT 9V to 18V, unless there are other regulations)

function description

General features

l9848 Integrated circuit is a single -chip integrated circuit, which provides high flexibility for driving medium loads. Eight outputs, 6 of which (output 1-6) can be used as a low-end or high-end drive of any combination, and two are special low-voltage side output (output 7-8). The device can be used to control the output through the SPI interface, thereby reducing the I/O port requirements of the microprocessor. In addition, the output 5-6 can be pwmed through external pins (input 5-6). The 8 -bit SPI input is used to command the 8 output drives to open or close, and add it to indicate the possible lock failure conditions that may occur. Multiple L9848 can be connected with an additional microprocessor I/O (CSN) of each device through the chrysanthemum chain. The implementation of self -configuration allows users to connect high or low -voltage side loads to these output terminals. L9848 will correctly drive them and provide correct fault mode operation without other inputs. The device switches the current within the temperature range of the variable load. The output is the MOSFET driver, with a minimized VDD current requirements. There is no VBATT input pin, but VBATT is connected to the drain of high -end output. When the power supply voltage that is applied to the output leakage is applied within the working range, it meets the specifications of all requirements. For the power supply voltage on the drain to 6.8V, the part is working normally, but it does not meet all parameter limit, that is, the output power -powered state voltage.

Output-Universal features

Six self-configured output (output 1-6) can drive incandescent lamps, inductive loads (non-PWMED), or biased VBATT resistance loads. These outputs are enabled and disabled through the SPI bus. Each output has a short-circuit current restriction and has an overheating protection described in the Functional Instructions-Heating . When the high-voltage side configuration output is connected to the instruction, the power supply voltage will become a smaller negative voltage (VBATT-45V). This is due to the cross -guidance of the design circuit and MOSFET. When the output of the instruction low -side configuration is turned off, after the command is opened, the output voltage will rise to the internal Zina clamp voltage (the minimum value of 40VDC) due to the rejuvenation of the inductive load.

-Outage 1-4

These four outputs can be used as high-voltage or low-voltage side drives. The pull -down method on the integrated current source locks the vacuum fault data correctly. These two current sources need to detect the opening load status because these outputs are configured as high -voltage or low -voltage side drives.

Drainage connection of output 1-4 (DRN1-4) is connected to the drain of the N-channel MOSFET transistor. The source of the output 1-4 (SRC1-4) is connected to the source of these pins to the N-channel MOSFET transistorEssence

-Output 5-6

These two self-configuration outputs can be used to drive high or low-side loads. In addition to these outputs controlled by the SPI bus, they can also be enabled and disabled through IN5 and IN6. IN5 and IN6 input and SPI command logically or to allow IN5-6 to input or start the SPI commands of these output. PWM control using IN5-6 on these outputs should only be performed under non-sensitive load. The integrated current source is pulled up and dropped to correctly lock the empty fault data. Both current sources need to detect one open, because these pins are connected to the drainage connection of high or low-side drive output ports 5-6 (DRN5-6).

Output 5-6 (SRC5-6) source connection

These pins are connected to the source of the N-channel MOSFET transistor.

-Output 7-8

These two outputs (DRN7-8) are dedicated low-end drives. Integrated current sources need to correctly lock the empty fault data.

Main power input (VDD)

VDD input is the main power of L9848. This power supply is used as the power logic circuit of all ITS and various other functions. Please note that if L9848 is connected to the processor that is running at a lower voltage (eg, 3.0 VDC), the microprocessor input connected to the L9848 will swing from 0 to 5.0 DC power.

Discrete input (IN5-6)

These inputs allow the output 5-6 through the external pin without using SPI. A logical 1 will enable the corresponding output regardless of the state of the SPI command register. The logic 0 is turned on if the SPI command register does not command the output to open, these inputs will disable the corresponding output. If the output is controlled only by SPI (internal drop -down), these pins can be kept open . These inputs are not sensitive loads for pulse width modulation (PWMED). This allows PWM control to not use SPI. TTL level compatible input voltage allows microprocessors to use 5.0V or 3.0V VDD power supply

serial peripheral interface (SPI)

A standard serial peripheral interface , A series (SCLK), data output (DO), data input (DI), and chip form a SELECT (CS) to allow the internal registers of the access to L9848. All outputs via this SPI. The input pin CS, SCLK, and DI have a TTL level compatible input voltage, allowing normal work to use 5.0V or 3.0V as a microprocessor with VDD power supply. The design of L9848 allows multiple L9848 chrysanthemum chains to further reduce the controller pinDemand.

- Serial data output (DO)

When CS is the logic 0 (low), the output pin is in a three -state state. When CS is a logical 1 (high), the pin always transmits 8 -bit data from the fault register to the digital controller. After the first 8 digits, the data is sent to the DO output, and then sends the digital data (before 8 SCLK cycles) that have been received in order. DO output continues to send 8 SCLK delay bits from DI to CS and finally convert data from logic 1 to logical 0 . Whether the data is changed after the SCLK declines, the status is 10NS or later. According to the definition, MSB (Table 3) is the last bit of the byte transmitted by DO and LSB from the logic 0 to the logic 1 .

- Serial data input (di)

When CS is high, this input obtains data from a digital controller. L9848 accepts the output of the 8 -bit data stream command to open or close. According to the definition, MSB (Table 1) is the byte received on DI. LSB is the last bit of each byte received on DI. Once CS is from logic 0 to logical 1 .

- Chip selection (CS)

This is the chip selection input pin. At the rising edge of the CS, the DO pin switches from three state to active output mode. When CS is high -electricity, the register data is moved and moved out of each subsequent SCLK from the DI and DO pins, respectively. In the decrease of the CS, the DO pin is switched back to the three state If the valid DI byte is received, the mode and fault register will be cleared . The valid DI byte definition is as follows: First, when the 8 -bit multiple is received, when the CS decreases, the second SCLK is lower. When the SCLK is low, the third current SPI cycle starts to meet the above 3 conditions. It will be cleared. The SCLK conversion must be seen before the CS is interpreted as the event. In order to re -load the fault register for enough time, the CS pin must be kept at least 1 μs, and then it becomes high again, and then starts to move the fault data on the DO pin. CS has an integrated fault filter that is used for 50ns or shorter (that is, no failure data and output 1-8 enable state). The CS is pulled down to GND.

- Serial clock (SCLK)

This is a clock signal input used to synchronize serial data transmission. DI data is transferred to DI to enter at the SCLK rising edge, and the data is changed at the SCLK decrease edge.

SPI DI input command register

Enter the byte (8 digits) to be routed to the command register. The content of the command register is given in the table 1 and Table 2. The additional DI data will continue to be wrapped on the foot. If CS will be suddenly sent after receiving the current bytes, this has just been sentSlightly

Failure operation

The fault diagnosis function includes an 8 -bit internal displacement register. Provide an open or short -circuit load detection by comparing the source or drain voltage and VDD voltage. When the output connection is closed as a low -voltage side device or a high -voltage side device, the opening load can be detected. When the output device connected to a low -voltage side device or a high -voltage side device is instructed to connect the short -circuit load, it can be detected. If the output 1-8 occurs short-circuit, open roads, or temperature is too high, the fault level of each channel will be set . The content of the fault register is shown in Table 3. The output load status of each individual channel defines Table 4 in the middle. If the opening and short -circuit meet the minimum duration standard, then re -lock it. If the thermal failure meets the duration standard after the CS becomes low , the heat failure will still be locked. The fault register can detect and lock multiple fault conditions (among 8 outputs) between clearing the fault logo. All faults will be cleared on the decline of chip selection (CS).

Initial fault register SPI cycle

After the first application of VDD to L9848, at

initial SPI cycle and all subsequent cycles The effective fault data will be output from the clock in the DO.

The bit of setting indicates which output is faulty.

- Cure lamp output

due to

light load. For example, the lamp load channel is enabled during a SPI cycle. About

After 20ms-100ms, a SPI cycle is required to read the correct fault locking data, which will be cleared

After the CS decrease of the CS of that SPI cycle.

Output 1-6 configuration

The drain and source of each output must be connected with one of the following two configurations (see

Figure 6A and Figures 6B).

-Low-end driver

When connecting any combination of 1-6 in the low-end drive configuration

Applicable output (SRC1-6) must be grounded. The drain (DRN1-

6) applicable to the output must be connected to the low end of the load.

-High-end driver

When any combination of output 1-6 is connected to the high-side driver configuration

Applicable output (DRN1-6) must be connected to VBATT. The source of the output

(SRC1-6) must be connected to the high-pressure side of the load.

The sensitivity of DRN1-6 to negative voltage transient

Any input that connects and is used for high-voltage side driveOut, the fast negative transient conversion rate will not accidentally issue POR (power -on reset) or cause parasitic atresia. However, in some cases

may need to have a 10nf to 100NF ceramic chip capacitor connected from the drain to GND to help

prevent very fast negative transients due to the equipment drainage pipe. And the problem happened.

Hot shutdown

Each 8 output has an independent thermal protection circuit. Once the temperature of the MOSFET device of the local N -channel MOSFET device reaches the ultra -temperature shutdown limit. Due to the lag of the opening and disable temperature levels, the fault passage shuts down and opens the periodic until the failure conditions are cleared, the ambient temperature is fully reduced or the output is commanded. Once any single channel enters the heat shutdown state, the logic 1 is locked to the fault register, if it meets the thermal fault filter (Note: Do not pass the road/short -circuit fault filter). Note: Due to the design of the L9848, the thermal limit of each output is not really independent. If an output is short -circuit, it may affect the operation of other output (because the horizontal heating in the mold). Users may need to monitor the fault level regularly. If a fault bit is set to the final output, and then the fault bit of other enabled output is set , and the user will send two SPIs to write cycles in 100ms. The first SPI writing cycle will remove the failure. If there are multiple in the second SPI writing cycle, the failure will be displayed, and these faults are likely to be a heat failure. The user will then disable this output recently enabled. Subsequently, the fault register should be asked to verify the correct operation of other output channels.

The charging pump uses

L9848 for each of the 6 configurable output channels to provide

low RDSON value as high During the side configuration, these oscillators work in a non -synchronous working mode. The frequency range of these charge pumps is designed to be higher than the band of the amplifier radio and below 8.0MHz, so that the harmonic will not enter the band of frequency regulating radio.

The waves formed

The opening and closing conversion rate of all output (output 1-8) are limited to reduce the energy in the conductive electromagnetic and capacitance vehicle beam. During the output drive, the characteristics of the switching voltage are linear and there is no interruption state conversion.

Por register initialization

If the VDD power supply increases from 0 to 5VDC within 0.3ms to 3ms, L9848 will wake up. L9848 has a Por circuit that monitors VDD voltage. When the VDD voltage reaches 4.1VDC and keeps at least 20 μs above the sliding level, the command and fault register are cleared . Before the VDD reaches the checkpoint, ensure that all eight outputs are closed. The valid POR and the VDD voltage occur than the effective highThe level, after reaching the required amount, the power of L9848 is fully controlled.If there is no output, the failure will be open , and there is no error failure to allow data to allow data on the DO output.

Anomalial voltage condition L9848 can still work normally under the following abnormal voltage conditions.

-Battery

Apply or applies or applied to the drain (DRN1-6) condensed or grounded (cold lights, snails) of the drain (DRN1-6) of the DRC1-6 by the load.Line tube, etc.).

-Maximum negative transient

This will force the output drainage pipe or power supply to be lower than module ground-20V.The ground offset L9848 is grounded and the chassis is grounded when it is directly connected to the high side load.If the driving low side load, there will be no offset between L9848 ground ground and load grounding.In addition, there may be -0.5V to 1.0V or ± VAC (10-200 Hz) between -0.5V to 1.0V or ± VAC (10-200 Hz) between the largest ground difference between the ground difference and connected to it.

- Lost ground operation

In the case of lfid L9848 module lost ground, any output is protected, active when the power is still connected.