Features

Low -current consumption: as low as 120 μA in the duty occupy ratio (typical value)

Wide power supply range: 2.3 volts to 5.5 volts [ 123]

programmable gain: 1 v/v to 128 v/v

programmable data rate: as high as 2 KSPS

20 SPS 16 -bit noise -free resolution

At the same time, inhibit 50Hz and 60Hz, 20 single -cycle digital filters

dual matching programmable current source: 50 μA To 1500 μA

Internal 2.048-V Reference: 5 ppm/° C (typical) drift

Internal 2%precision oscillator

#8226; Internal temperature sensor: 0.5 ° C (typical value) accuracy

two differential or four single-end inputs

SPI #8482; compatible compatibility Interface

Packaging: 3,5-mm × 3,5-mm × 0,9-mm qfn

temperature sensor :

-The thermocouple thermometer

-The resistor -type temperature detector (RTD) 2, 3 or 4 line type

bridge sensor [ 123]

Portable Instrument

Factory automation and process control

Explanation

ADS1120

is a precision The 16 -bit modulus converter (ADC) provides many integrated functions to reduce the number of components in the application of system costs and measure the application of small sensor signals. This device has two differential or four single -end inputs, and through a flexible input multi -path reuse (MUX), a low noise, programmable gain amplifier (PGA), two programmable excitation current sources, a reference voltage Source, an oscillator, a low -pressure side switch and a precision temperature sensor.

The device can be converted at the data rate of 2000 samples (SPS) per second with a single cycle. In 20 SPS, digital filter provides industrial applications that suppress noise at the same time at the same time. The internal PGA provides an increase of up to 128 V/V. This PGA makes the ADS1120 very suitable for measuring the application of small sensor signals, such as the resistor temperature detector (RTD), thermocouple, thermal resistance and bridge sensor. When using PGA, it should beThe device supports the measurement of the pseudo -separation or full differential signal. Alternatively, this device can be configured to bypass the internal PGA while providing high input impedance, and obtain a 4V/V gain, allowing single -end measurement. When working in a duty -occupying ratio of PGA, the power consumption is as low as 120 μA. Establish a communication with device through mode 1 SPI compatibility interface. The ADS1120 is encapsulated with lead-free QFN-16 or TSSOP-16, and its temperature range is -40 ° C to+125 ° C.

Order information

For the latest software packages and order information, please refer to the software package appendix at the end of this document.

SPI timing characteristics

(1), in TA - 40 ° C to+125 ° C, DVDD 2.3 V to 5.5 V, dual load 20 pf | 10 kΩ to DGND, unless otherwise explained.

(2), if you do not send a complete command in 13955 · TMOD (normal mode, duty -occupied ratio) or 27910 · TMOD (turbine mode), serial interface reset, the next SCLK pulse starts to start a new new pulse starts to start a new new pulse. The communication cycle. TMOD 1/FMOD. When using an internal oscillator or an external 4.096-MHz clock, the modulator frequency (FMOD) is 256 kHz in the normal and duty cycle mode, and 512 KHz in the Turbo mode.

Typical features

In TA +25 ° C, AVDD 3.3 V, AVSS 0 V, use external VREF 2.5 V to enable PGA, unless there are other instructions.

Noise performance performance Delta-sigma (Δ∑) modulus converter (ADC) is based on over-sampling principle. Δ 输Adc's input signal is sampled at high frequency (modulator frequency), and then filter and extract in the digital domain to generate conversion results at the corresponding output data rate. The ratio of the frequency of the modulation to the output data is called an over -sampling ratio (OSR). By increasing the OSR to reduce the output data rate, the noise performance of ADC can be optimized. In other words, when the output data rate is reduced, the noise of the input end is reduced, because more diversity samples of the internal modulation are average to generate a conversion result. Increasing gain can also reduce the input reference noise, which is particularly useful when measuring low level signals. Table 1 to Table 4 summarizes equipment noise performance. Use internal 2.048-vThe benchmark, the data represents the typical noise performance of the TA +25 ° C. The displayed data is the result of the average reading of a single device within about 0.75 seconds, and measured in the case of short circuit inside the input end. Table 1 and Table 3 list the input reference noise (unit: μVRMS) under the conditions. Please note that the μVPP value is displayed in parentheses. Table 2 and Table 4 list the corresponding data calculated from the μVRMS value (ENOB). Note that the noiseless bit of noise from peak to peak noise value is displayed in brackets. Input reference noise (Table 1 and Table 3) only occurs slightly when using the external low noise benchmark (such as Ref5020). When using the reference voltage other than 2.048 V, calculate the number of ENOB and noiseless position, please use Formula 1 to Formula 3:

ENOB Ln (full marking range/VRMS noise)/Ln (2) (2) (2)

Noise no sound position ln (full marking range/VPP noise)/ln (2)

Full marking range 2 · VREF/gain

Overview

ADS1120 is a small, low power consumption, 16 -bit Δ∑ADC, which provides many integrated functions, which measures small sensor signals In applications, the number of system costs and components can be reduced.

In addition to the core and single -cycle stable digital filter, the device also provides low noise, high input impedance, programmable gain amplifier (PGA), internal benchmark voltage source and clock oscillator. This device also integrates a highly linear and accurate temperature sensor, as well as two matching programmable current sources (IDACs) for sensor excitation. All these characteristics are designed to reduce the external circuits required in typical sensor applications and improve the overall system performance. An additional low -voltage side power switch simplifies the design of low -power bridge sensor applications. The device is fully configured through four registers and controlled by 6 commands through mode 1 SPI compatibility interface. Figure 37 shows the function box diagram of the device.

ADS1120ADC measures a differential signal vin, which is the voltage difference between node AINP and AINN. The core of the converter consists of a differential switching capacitor, Δ∑ modulation, and digital filter. Digital filter receiving high -speed ratio from the modulator and the proportion of the input voltage to the input voltage from the modulator. This structure will produce a very strong attenuation in any co -mode signal.

This device has two useful conversion modes: single -round and continuous conversion mode. In a single trigger mode, the ADC executes a conversion of the input signal according to the request and stores the value in the internal data buffer. Then the device enters the low power consumption state to save electricity. The single start -up mode is designed to be only neededThe regular conversion system provides a significant energy -saving effect, or has a long free time between conversion. In the continuous conversion mode, once the last conversion is completed, the ADC will automatically start the transformation of the signal. The new data is available at the programming data rate. You can read data at any time without having to worry about data damage and always reflect the recently completed conversion.

Multi -path reuse

The device contains a very flexible input multi -way reused, as shown in Figure 38. A combination of four single -end signals, two differential signals or two single -end signals and one differential signal. Multi -path reusopter is configured by the four -bit (MUX [3: 0]) in the configuration register. When measuring a single -end signal, the negative ADC input (AINN) is connected to AVS through the switch in the internal multi -way reuse. For system monitoring purposes, you can choose an analog power supply (AVDD -AVSS)/4 or the current selected external reference voltage (VREFPX -vrefnx)/4 as an ADC input. Multi -path reuse can also use any route in the two programmable current sources to any analog input (AINX) or any dedicated reference pin (Refp0, Refn0).

to AVDD and AVSS static discharge discharge (ESD) diode protection input. To prevent the ESD diode from opening, the absolute voltage of any input end must be kept within the range of equivalent 4:

If the voltage on the input pin may violate these conditions, then It may be required that the external Schutki clamping diode or series resistor to limit the input current to the security value (see the absolute maximum rated value table). Unused inputs on over -driving devices may affect conversion on other input pins. If there may be any drivers in the input that is not used, TI is recommended to use the external Schottky diode to restrain the signal.

Low noise pga

This device has low noise, low drift, high input impedance, programmable gain amplifier (PGA). PGA can be set to 1, 2, 4, 8, 16, 32, 64, or 128. The three -bit (gain [2: 0]) in the configuration register is used for configuration gain. The simplified picture of the PGA is shown in Figure 39. PGA is composed of two cut wave stable amplifiers (A1 and A2) and a resistor feedback network that sets a PGA gain. PGA input is equipped with electromagnetic interference (EMI) filters.

VIN represents the difference input voltage vin (Vainp - Vainn). The gain of PGA can be calculated through Formula 5:

The gain is changed by switching the different values u200bu200bof RG. The input voltage range of PGA is defined by the reference voltage of the gain setting and use of the input voltage (FS), as shown in the equivalent 6:

123]

Table 5 shows the corresponding scale range when using the internal 2.048-v benchmark.

In order to maintain the linear working range of PGA, the input signal must meet certain requirements discussed in this section.

The output of the two amplifiers (A1 and A2) in FIG. 39 cannot swing to a position of more than 200 MV from a distance power supply (AVSS and AVDD). If the distance between the output end and the output terminal driver is less than 200 millivoltors, the amplifier will be saturated and becomes non -linear. This condition means that the output voltage must meet the square program 7:

In order to derive the voltage equation of the output end (OUP and OUTN) Methods. Because PGA is symmetrical design, this separation can be completed. Therefore, the gain setting the resistor (RG) must be divided by 2, and all the voltage at the horizontal cutting point must refer to the common modulus voltage (VCM), as shown in Figure 40.

The voltage of the PGA input terminal (AINP and AINN) can be represented as Formula 9 and Formula 10:

[ 123] Output voltage (Voutp and Voutn) can be calculated according to type 11 and type 12 calculations:

The output voltage of the amplifier A1 and A2 can also be used Formula 11 and Formula 12 converted to the requirements of the input co -mode voltage range. Formula 13 and Formula 14 gave these requirements:

In order to calculate the minimum and maximum common modulus voltage limit, Value must use the maximum differential input voltage (VIN (MAX)) in the application, which is not necessarily a possible FS range.

Due to the specific design of PGA, the smallest VCM must also meet the Archives 15.

Note

The common model voltage requirements are as follows:

Figure 41 and Figure 42 display AVDD 3.3 V and AVSS 0 V (gain 1 and gain 16) The figures of the co -mode voltage limit value.

The discussion below explains how to apply Formula 13 to Formula 15 to the assumption application. The setting of this example is avdd 3.3 V, AVSS 0 V, gain 16, use external reference, VREF 2.5 V. Then, the maximum possible differential input voltage vin (Vainp ～ Vainn) that can be applied is limited at fs ± 2.5 v/16 ± 0.156 V's full marking range. Therefore, Formula 13 to Formula 15 draws the allowable VCM range to be 1.45 V ≤VCM ≤ 1.85 V.

For example, if the input sensor signal connected to the assumption application does not use the entire standard range, but is limited to the range of vin (max) ± 0.1 v, the reduced input that reduces the reduced input The signal amplitude relax the VCM limit to 1.0 V ≤VCM ≤ 2.3 V.

In the case of a full differential sensor signal, each input (AINP, AINN) can swing near the co -mode voltage (Vainp+Vainn)/2 to ± 50 mv. The voltage must be kept at 1.0 V and and 2.3 between V. The output of the symmetrical Whist Bridge is an example of a full differential signal.

In comparison, the signal of the resistor -type temperature detector has a pseudo -difference point (such as the execution of the RTD measurement part), where the negative input is kept in the constant voltage other than 0 V. Only the voltage at the positive input end occurs. Variety. When the pseudo -difference signal must be measured, the negative input in this example must be biased between 0.95 V and 2.25 V. Then, the positive input can swing on the negative input to VIN (MAX) 100 MV. Note that in this case, the changes in the co -mode voltage occur at the same time as the changes in the positive input voltage. In other words, when the input signal fluctuates between 0V ≤Vin≤Vin (MAX), the co -mode voltage fluctuates between Vainn ≤Vainn+ #189; vin (MAX). Meet the co -mode voltage requirements of the maximum input voltage VIN (MAX) to ensure that the requirements are met in the entire signal range.

FIG. 43 and Figure 44 showed examples of full differential and pseudo -difference signals, respectively.

Bypse PGA

At the gain of 1, 2 and 4, the device can be configured to disable and bypass low noise PGA. The disable PGA can reduce the total power consumption, and it also eliminates the restrictions of the equivalent 13 to equation 15 for the total model input voltage range VCM. When the PGA is disabled, the absolute and common mode input voltage range is (AVSS – 0.1 v ≤Vainx, VCM ≤avdd+0.1 V). To measure the single -end signal of AVSS (AINP VIN, Ainn AVSS), PGA must be bypassed.

When PGA is disabled by setting up PGA_ by the configuration register, the device uses buffer switch capacitor grade to obtain gain 1, 2 and 4. The internal buffer in front of the switching capacitor level ensures that the capacitor is filled with the least effect on the input load. When PGA is disabled, the typical value of absolute input current (flowing or out of the current) and differential input current (the absolute current between positive and negative inputs) are referred to Figure 20 to Figure 25.

High output impedanceThe signal source, external buffer is still necessary. Please note that the active buffer will introduce noise, and also introduce offset and gain errors. All these factors should be considered in high -precision applications.

Moder

ADS1120 uses Δ∑ modulator to convert an analog input voltage into pulse encoding modulation (PCM) data stream. The modulator runs in the normal and the duty cycle mode in a modem clock frequency of FMOD FCLK/16. In the Turbo mode, FMOD FCLK/8 is provided by the internal oscillator or external clock source. Table 6 shows the frequency of each mode of each mode using an internal oscillator or a 4.096 MHz external clock.

Digital filter

This device uses a linear phase limited pulse response (FIR) digital filter to filter and filter the digital data stream from the regulator and Exclude. Digital filters can automatically adjust according to different data rates and always stabilize within a cycle. When the data rate is 5 SPS and 20 SPS, the filter can be configured to refuse 50 Hz or 60 Hz line frequency, or at the same time reject 50 Hz and 60 Hz. Two bits (50/60 [1: 0]) in the configuration register are used to configure the filter accordingly. When using an internal oscillator or an external 4.096-MHz clock, the frequency response of the digital filter is shown in Figure 45 to 58.

Note

If the frequency of use is not 4.096MHz's external clock, the change of the filter trap and clock The frequency is proportional. For example, if the 2.048-MHz clock is used, the 4.096-MHz clock appears at 10 Hz when the 4.096-MHz clock appears at 10 Hz.

Output data rate

Table 7 shows the actual conversion time of each data rate settings. The value provided is represented by the TCLK cycle of the outer clock with the clock frequency FCLK 4.096 MM. If the frequency of use is not an external clock with 4.096MHz, the data rate will be zoomed proportionally.

The data rate of continuous conversion mode decreases from time to a drop edge to the next DRDY decrease. The first SCLK decrease of the START/SYNC command was first started to start 210 · TCLK (normal mode, duty cycle mode) or 114 · TCLK (turbine mode).

The data rate of the single-artillery mode decreases from the final SCLK decrease of the last SCLK command of the Start/Sync command to the DRDY decrease edge, and enters the next TCLK in four houses and five. If you use an internal oscillator, you must add up to 50 μs (normal mode, duty -occupying mode) or 25μs (vortexWaking time of extra oscillator in the wheel mode). The internal oscillator starts power at the first SCLK rising edge of the start/synchronization command. If the SCLK frequency that is higher than 160 kHz (normal mode, duty -occupying ratio) or 320 kHz (turbine mode), the oscillator may not be fully powered at the end of the start/synchronization command. The ADC then wait until the internal oscillator is fully powered, and then starts to change. The single -round conversion time in the duty cycle mode is the same as in normal mode. For more detailed information about the operation of the duty cycle mode, please refer to the duty cycle mode part.

Please note that even if the conversion time under 20-SPS settings is not exactly 1/20 Hz 50 ms, this difference does not affect 50 Hz or 60 Hz suppression. In order to achieve the prescribed 50 Hz and 60 Hz suppression, the external clock frequency must ensure that it is 4.096 MHz.

Mixing

Like any sampling system, if there is no appropriate anti -aliasing filtration, mixing may occur. When the frequency component of half of the ADC sampling frequency (also known as the Nyquist frequency) is folded and displayed in the actual frequency band of the sampling frequency, it will occur. Note that in Δ∑Adc, the input signal is sampled by the modulator frequency FMOD instead of the output data rate sampling. The filter of the digital filter responds to the multiple of the sampling frequency (FMOD), as shown in Figure 59. When the signal or noise reaches the frequency of repeating the filter, the digital filter is attenuated. Unless the external analog filter is attenuated, any frequency component existing in the input signal around the modulator or the periphery of the multiples will not be attenuated, so that the frequency band is interested in interest. Some signals inherently restrictions on bandwidth; for example, the output change rate of thermocouple is limited. However, these signals may contain noise and interference ingredients at a higher frequency, and these ingredients can be folded back to the frequency bands of interest. A simple RC filter (in most cases) is enough to inhibit these high -frequency components. When designing input filter circuits, you must consider the interaction between the input impedance of the filter network and the ADS 1120.

Voltage benchmark

This device provides integrated low drift, 2.048-v reference. For applications that require different reference voltage values u200bu200bor ratio measurement methods, the device provides two differential reference inputs (REFP0, Refn0 and Refp1, Refn1). In addition, analog power supply (AVDD) can be used as a reference. Differential reference input allows reference to free -moving voltage freedom. Refp0 and Refn0 are dedicated reference inputs, while REFP1 and Refn1 are shared with input AIN0 and AIN3, respectively. Reference input is internal buffer to increase the input impedance. Therefore, when using external benchmarks, no additional participation is usually requiredThe test buffer, and when it is used for ratio measurement application, the benchmark input does not load any external circuit. The reference source is selected by the two (VREF [1: 0]) in the configuration register. By default, the internal reference is being selected. After power -on, when the power -off mode is exited or switched from the external reference source to the internal reference source, the internal reference voltage needs to be less than 25 μs before it can be completely stable.

Clock source

The equipment system clock can be provided by the internal low drift oscillator, or it can be provided by the external clock source entered on the CLK. CLK pin is connected to DGND before power -on or reset to activate the internal oscillator. After detecting the two rising edges on the CLK tube foot, connect the external clock to the CLK tube foot at any time to cause the internal oscillator to lose. The device then runs on the outside clock. After the ADS1120 is switched to the outer clock, if the power supply is not recycled or the reset command is sent, the device will not be able to switch back to the internal oscillator.

Inspirational current source

The device provides two matching programmable excitation current sources (IDAC) for RTD applications. The output current of the current source is programmable for 50 μA, 100μA, 250 μA, 500 μA, 1000 μA or 1500 μA, and uses the corresponding position in the configuration register (IDAC [2: 0]). Each current source can be connected to any analog input (Ainx) and any dedicated reference input (REFP0 and Refn0). The two current sources can also be connected to the same tube foot. IDAC's route is configured by bits in the configuration register (i1mux [2: 0], i2mux [2: 0]) configuration. Be careful not to exceed the compliance voltage of IDACS. In other words, the voltage on the foot of the IDAC wiring should be limited to (AVDD -0.9 V), otherwise it will not meet the specified IDAC current accuracy. For the application of a three -line resistor temperature detector, the matching current source can be used to eliminate errors caused by the sensor's binding resistor (for detailed information, see the RTD measurement section).

After using the bitc [2: 0] to program the IDAC current as the corresponding value, the IDAC needs up to 200 μs to start. If the configuration register 2 and 3 are not written during the same WREG command, TI recommends using the bitac [2: 0] to set the IDAC current to the respective value, and then select the routing for each IDAC (I1MUX [2: 0] , I2mux [2: 0]).

In a single trigger mode, if the IDAC [2: 0] bit is set to a non -000 value, the IDAC maintains the activity status between any two conversion. However, when the PowerDown command is issued, IDAC is powered off.

Sensor detection

In order to help detect possible sensor failures, the device provides internal 10-μA burning current source. PassWhen setting the corresponding bit (BC) in the register to enable, one current source inputs the current into the currently selected positive analog input (AINP), and the other current source absorbs the current from the selected negative model input (AINN).

In the case of the sensor's road, these burn -of -cooked current sources pulled the positive input to AVDD, and the negative input was pulled to the AVSS to generate a full -scale reading. Full margin reading may also indicate the lack of sensor overload or benchmark voltage. Near the zero reading may indicate the short circuit of the sensor. Note that the absolute value of the burning current source usually changes ± 10%, and the internal multi -channel relicner adds a small series resistor. Therefore, it is difficult to distinguish the sensor short circuit from normal reading, especially when the input terminal uses an RC filter. In other words, even if the sensor is short -circuited, the voltage drop of the remaining resistance of the external filter and the remaining multi -road relics will cause the output read to be higher than zero.

If the short -circuit detection of the sensor requires a higher accuracy current source, TI is recommended to use the excitation current source (IDAC). Keep in mind that when the burning current source is enabled, the ADC reading of the function sensor may be damaged.

Low -voltage side power switch

In the simulation input AIN3/Refn1 and AVSS, a low -voltage -side power switch with low -voting resistance is also integrated. This power switch can be used to reduce the system power consumption in bridge sensor applications. The method is to cut off the circuit between the bridge between the conversion. When setting the corresponding position (PSW) in the register, the switch is automatically closed when the start/synchronization command is sent, and it is turned on when the power -off command is issued. Note that if the PSW bit is set to 1, the switch is kept closed between a single trigger mode. By setting the PSW bit to 0, the switch can be turned on at any time. By default, the switch is always turned on.

System monitor

This device provides monitoring methods for AVDD simulation power and external reference voltage. To select any monitoring voltage, internal multi -road relics (MUX [3: 0]) must be configured in the configuration register. When using the monitoring function, regardless of the configuration register set, the device automatically bypass PGA and sets the gain to 1. Please note that the function of the system monitor only provides rough results, which does not mean precise measurement.

When measured the simulation power supply (MUX [3: 0] 1101), the transition obtained is about (avdd -avss)/4. Regardless of what reference source is selected in the configuration register (VREF [1: 0]), the device uses the internal 2.048-V benchmark for measurement.

When one of the two possible external reference voltage sources (MUX [3: 0] 1100) monitors two possible external reference voltage sources (MUX [3: 0] 1100), the result is about (VREFPX -vrefnx)/4. Refpx and Refnx represent the external reference input pair selected in the configuration register (VREF [1: 0]). The device automatically uses internal benchmark to testquantity.

Disposal calibration

Internal multi -way relics provided PGA input (AINP and AINN) to the options with PGA input (AINP and AINN) to the middle power supply (AVDD+AVSS)/2. This option can be used to measure and calibrate the offset voltage of the device. The method is to store the results of the short -circuit input voltage reading in the microcontroller, and then subtract the result from each reading. TI recommends reading multiple reading in the case of short circuit input and average of the results to reduce the impact of noise.

Power

The device requires two power supply: analog (AVDD, AVSS) and numbers (DVDD, DGND). The simulation power supply can be dual -pole (for example, AVDD +2.5 V, AVSS --2.5 V) or a single power supply (eg, AVDD +3.3 V, AVSS 0 V), and independent of the digital power supply. Digital power supply sets the digital input/output level. The power supply can be arranged in any order, but in any circumstances, any simulation or digital input shall not exceed their respective simulation or digital power supply voltage restrictions.

Temperature sensor

When the TS bits in the configuration register are enabled, the temperature measurement mode of the device is configur