Features

4 ADCs are installed in a packaging

Code serial digital output, each channel has ECC

The temperature sensor on the film

95 DB channels are disturbing

signal -to -noise ratio 65 dbfs, ain 85 mHz, 250 mSPS

sfdr 77 dbc, Ain 85 MHz, 250 MSPS

Excellent linearity

dnl ± 0.3 lsb (typical)

inl ± 0.7 lsb (typical)

780 MHz full power simulation bandwidth

Power dissipation 380 MW per channel, 250 MW/s

1.25 V p-p input voltage range, which can be adjusted to 1.5 V p-p

1.8 V power operation

The clock occupation ratio stabilizer

The serial port interface has a power -off mode

Digital test mode enables

Programming pin function (PGMX, PDWN)

Application

Communication receiver

cable head-end device/M-CMTS

Broadband radio

Wireless infrastructure transceiver

radar/military aerospace subsystem

Test equipment

General description

AD9239

It is a four -bit, 12 -bit, 250 MSPS modulus converter (ADC) with a temperature sensor and high -speed serial interface on the film. Its design supports digital high -frequency and wide -moving signals to enter a bandwidth up to 780 MM. The output data is serialized and presented in a package format, including channel specific information, coding samples, and error correction code.

ADC requires a 1.8V power supply, and the input clock can be driven with sine waves, LVPECL, TTL or LVDS. The clock duty cycle stabilizer allows high performance to score at full speed and extensive clock duty. The benchmark on the film eliminates the needs of external decoupling and can be adjusted through SPI control.

Support multiple power -off and standby mode. When the standby operation is enabled, the digital link is still running, and the ADC usually consumes 145 MW per channel.

AD9239 is manufactured by advanced CMOS technology, and a leading 72 -free 72 -drawing LFCSP packaging is used. The industrial temperature range is 40 ° C to+85 ° C.

Product Highlights

1. Four ADCs are included in a small packaging saving space.

2. PLL on the film allows users to provide a ADC sampling clock, and the PLL allocation and double increase to generate the corresponding data rate clock.

3. Coding data rate supports up to 4.0 Gbps per channel. Codes include biases to ensure the correct DC co -mode, embedded clock and error correction.

4.AD9239 is powered by a 1.8 volt power supply.

5. Flexible synchronization scheme and programmable mode pin.

6. The temperature sensor on the film.

Figure Figure

Sequence diagram

Absolute maximum rated value

The stress that exceeds the absolute maximum rated value may cause permanent damage to the device. This is just a stress rated value; it does not imply that the device's functional operations described in the operation part of this specification or any other conditions. Long -term exposure to absolute maximum rated conditions may affect the reliability of the device.

Thermal resistance

The exposed leaves must be welded into the ground layer of the LFCSP package. The exposed paddle leaf welding is added to the client board to increase the reliability of the welding joint, and the maximum heat capacity of the packaging is increased.

The typical θja, θja, and θja values are specified for 4 layers in the static air. Increased heat dissipation, effectively reduce θJa. In addition, the metal that was directly contacted with the packaging was led by the metal traces, holes, grounding, and power planes, reducing θja.

典型性能特征

[123 ] Equivalence circuit

Operating theory ) Composition of the assembly and switch capacitance ADC. In digital correction logic, the quantitative output of each level is combined into the final 12 -bit result. The assembly line structure allows the first level to operate the new input sample, while the rest of the previous stage operates the previous samples. The sampling occurs at the rising edge of the clock.

Each level of the pipeline (excluding the last level) is composed of low -resolution Flash ADC connected to the switch capacitor DAC and the remaining amplifier (eg, multiplication digital modulus (MDAC)). The remaining amplifier enlarged the restructureThe difference between h input. Each stage is used to use a digital correction that facilitates flash memory errors. The last level consists of a Flash ADC. The input level contains a differential SHA, which can communicate or DC coupling in differential or single -end mode. The output of the pipe ADC is converted from the data serializer, encoder and CML driver block to the final serial format. Data rate multiplier creation is created to output high -speed serial data at the CML output end.

Precautions for analog input

The analog input of AD9239 is a differential buffer. The input is optimized to provide excellent broadband performance and requires analog input to drive differential driving. If a single -end signal -driven simulation input is used, the signal -to -noise ratio and signal -to -noise ratio performance will decline.

In order to obtain the best dynamic performance, the source impedance of VIN+X and VIN x is matched to make the co -mode stability error symmetrical. These errors are reduced by ADC's co -mode suppression. Each input of a small resistor can help reduce the peak transient current injected from the drive source input level.

In addition, low Q [sensor or iron oxygen magnetic beads can be placed on each branch of the input to reduce the height difference capacitance of the analog input terminal, thereby achieving the maximum bandwidth of ADC. When the front end of the high -frequency (IF) driver variable degenea, you need to use a low q electromoter or iron oxygen magnetic bead. One parallel container or two single -end capacitors can be placed on the input end to provide a matching non -passive network. This eventually generates a low -pass filter at the input end to limit unnecessary broadband noise. See the AN-827 application description and simulation dialogue article The transformer coupling front end of the broadband A/D converter (Volume 39, April 2005) to obtain more information about this theme. Generally, the accuracy value depends on the application.

By setting the ADC to the maximum span in the differential configuration, the maximum signal -to -noise ratio can be achieved. For AD9239, the default input range is 1.25 V p-P. To configure ADC for different input range, see the register 18. In order to obtain the best performance, 1.25 V p-P or larger input range should be used.

Differential input configuration

There are several methods that can actively or passively drive AD9239; in any case, the optimal performance can be achieved through differential driving simulation inputs. For example, using the ADA4937 differential amplifier to drive AD9239 as the baseband and the second Nequest (~ 100 MHz IF) application provides excellent performance and flexible ADC interfaces (see Figures 45 and Figure 46). In any application, 1%resistance is applied to a good gain matching. It should also be noted that the DC coupling configuration will display some degeneration of the bruises. For further reference, see the ADA4937 data table.

For the application of the signal -to -noise ratio is the application of a key parameter, the coupling of differential transformers is a recommended input configuration (see Figure 47 to Figure 49) to achieve the real performance of AD9239.

Regardless of the configuration, the value of the parallel container C depends on the input frequency and may need to be reduced or removed.

Single -end input configuration

Single -end input can provide sufficient performance in the cost -sensitive application. In this configuration, SFDR and distortion performance will be reduced due to the input co -mode swing. If the application requires a single -end input configuration to ensure that the source resistance of each input end is good to achieve the best performance. When VIN X pins are terminated, the full marker input of 1.25 V p-p can be applied to the VIN+X pins that can be applied to ADC. Figure 51 detailed the typical single -end input configuration.

Clock input Note

In order to obtain the best performance, AD9239 sample clock input (CLK+and CLK-) should use differential signals to control clocks. This signal is usually coupled to CLK+and CLK-pins through transformers or capacitors. The internal bias of these pins is 1.2V without extra bias.

FIG. 52 shows the preferred method for the AD9239 timing. The low jittering clock source uses a radio frequency transformer to convert from a single -end signal to a differential signal. Back-TOBACK-SCHOTTKY diode passing through the second transformer will enter the clock offset of AD9239 to a P-P difference of about 0.8V. This helps to prevent the large voltage fluctuations of the clock through other parts of the AD9239, and maintain the rapid rise and decrease of the signal, which is essential for low shake performance.

Another option is to communicate with the PECL signal to the sample clock input pin, as shown in Figure 53. AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9518 series clock driver provides excellent jitter performance.

In some applications, the input of the sampling clock in the sampling clock with a single -end CMOS signal is acceptable. In this application, CLK+should be driven directly from the CMOS gate, and the CLK-pin should be connected with a 39kΩ resistor with a 0.1 μF capacitor (see Figure 55). Although the CLK+input circuit power supply is AVDD (1.8 V), the input design is the input voltage that can withstand up to 3.3 V.

The clock considering factors

] Typical high -speed ADC uses two clock edges to generate various internal timing signals. Therefore, these ADCs may be very sensitive to the clock duty ratio. Generally, the clock duty ratio requires a 5%tolerance to maintain dynamic performance characteristics.

AD9239 contains a duty duty stabilizer (DCS), which provides an internal clock signal with a 50%rated duty cycle when the non -sampling edge is redirected. In this way, the width -range clock input duty cycle can be achieved without affecting the performance of AD9239. When the DCS is turned on (default), the noise and distortion properties have almost no change within a large duty cycle. However, some applications may need to turn off the DCS function. If so, remember that in this mode, the dynamic range performance may be affected. For more detailed information about using this function, see the memory mapping part.

The jitter of the input end rising edge is an important problem. The internal stable circuit does not reduce this jitter. The duty cycle control circuit does not work when the clock frequency below 50 MHz nominal clocks does not work. It is not recommended that this ADC clock is dynamic. The dynamic movement clock requires a long waiting time so that the rear -end serial capture is redirected and re -synchronized to the receiving logic. This long -term constant far exceeds the time required for DSC and PLL locking and stability. Only in a few cases, it is necessary to disable the DCS circuit of register 9 (see Table 14). It is recommended to keep the DCS circuit in order to maximize the exchange performance.

Clock jitter precautions

High -speed, high -resolution ADC is very sensitive to the quality of clock input. Under a given input frequency (FA), the decrease in signal -to -noise ratio caused by pore diameter shake (TJ) can be calculated through the following formulas:

In this equation, in this equation, in this equation, in this equation, in this equation, in this equation, in this equation, in this equation, in this equation, The RMS pore jitter represents the average root root of all jittering sources, including clock input, analog input signal, and ADC aperture jitter. It is particularly sensitive to jitter if the lack of sampling applications (see Figure 57).

In the case of the aperture jitter that may affect the dynamic range of AD9239, the clock input should be regarded as an analog signal. The power supply of the clock driver should be separated from the ADC output drive power to avoid using digital noise to modify the clock signal. Low jitter, crystal control oscillator is the best clock source. If the clock is generated from another type of source (through the selection, division, or other methods), the original clock should be reused in the last step.

Please refer to the AN-501 application instructions, An-756 application.

Power loss

As shown in Figure 58 to 60, the power consumed by AD9239 is proportional to its clock frequency. Digital power consumption is not great, because it is mainly determined by the bias current of the DRVDD power supply and digital output drive.

Digital startup order

The digital data output from AD9239 are encoded and packaged, which requires the device to have a certain start order. Users should initialize the following steps in order to capture relevant data at the receiving logic.

1. Be initially softened by the bit 5 of the register 0 (see Table 14).

2. By default, the automatic initialization of all PGMX tube feet into a synchronous pipe foot. These pins can be used to lock FPGA timing and data capture during the initial launch. These pins correspond to each channel (pgm3 channel A).

3. Each synchronous pipe foot is kept at a low level until its respective PGMX tube feet receives high signal input from the receiver. During this period, ADC outputs a training mode.

4. The training mode defaults to the value implemented in register 19 to register 20.

5. When the receiver finds the frame boundary, the synchronous logo is terminated by synchronous tube foot or SPI. ADC output valid data on the next group boundary. The time required for the establishment of synchronization is highly dependent on the logic processing of the receiver. See the switch specification section; the switch is directly related to the ADC channel.

6. Once the steady -state operation of the device occurs, these pins can be allocated to the backup option by using the register 53 (see Table 14). All other tube feet serve as universal synchronous pipes.

In order to minimize the deviation and time deviation between each channel output, the following measures should be taken to ensure that each channel packet packet is within the ± 1 clock cycle of its specified exchange time. This is not necessary for some receiver logic.

1. Power off completely through the external PDWN pin.

2. Tablet chip through external reset pins.

3. By releasing the external PDWN pins, the power supply is restored.

Digital output and timing

AD9239 has different digital output, and power is powered by default. Drive current exports on the chip and sets the output current of each output to nominal 8mAh. Each output has a 100Ω dynamic internal terminal to reduce unnecessary reflection. A 100Ω differential terminal resistor should be placed at the input end of each receiver to swing at the receiver 800 MV P-P. Alternatively, you can use a single -end 50Ω terminal. When a single -end terminal is used, the terminal voltage should be DRVDD/2; otherwise, the AC coupling conjugate container can be used to connect any single -end voltage.

AD9239 digital output can be used as a customized integrated circuit (ASIC) and on -site programming door array (FPGA) receiver interface to provide excellent switching performance in the noise environment. It is recommended to use a single -point -to -point network extensionPut, place a 100Ω differential terminal resistor at the position close to the receiver logic. If the DC coupling connection is used, the co -mode of the digital output automatically bias itself to half of the receiver's power supply (that is, for the 1.8 V receiver power supply, the co -mode voltage is 0.9 V). For the logic of the receiver that is not within the range of the DRVDD power supply, a communication coupling connection should be used. Just place a 0.1 μF capacitor on each output pin, and lead a 100Ω differential terminal at a position near the receiver side.

If there is no long -term receiver terminal or differential tracking route, it may cause timing errors. In order to avoid such timing errors, it is recommended that the length of the record channel is less than 6 inches, and the differential output record can be approached, and the length is equal.

Figure 63 shows the digital output (default) data eye and time interval error (TIE) jitter on the standard FR-4 material The histogram, the length of the record is less than 6 inches. Figure 64 shows the length of the length of the standard FR-4 material. Please note that the TIE JITTER histogram reflects the decrease in the openness of the data eyes when the edge deviates from the ideal position. When the length of the trace line exceeds 6 inches, the user has the responsibility to determine whether the waveform is in line with the timing budget of the design.

The additional SPI option allows users to further increase the voltage of the output drive of all four output to drive longer records (see registers in Table 14). Although this will generate a larger rise and decrease time at the edge of the data and it is not easy to error, the power consumption of the DRVDD power supply will increase when using this option. For more details, see the memory mapping part.

The format of the output data is defined as the offset binary. For example, the output encoding format is shown in Table 8.

To change the output data format to TWOS supplement or Gray code, see the memory mapping part.

Data from each ADC are serialized and provided on a separate channel. The data rate of each serial stream is equal to N bit multiplied by multiplied by the sampling clock rate. In addition, it is necessary to consider some expenses of the 8 -bit header and error correction. To. The lowest typical clock rate is 100 millisecond/second. For the clock rate below 100 millisecond/second, see the register 21 in the SPI memory mapping. This option allows users to adjust the PLL loop bandwidth in order to use the clock rate as low as 50MSPS.

Register 14 allows users to reverse digital output from its nominal state. This should not be confused with turning the serial flow into the LSB-FIRST mode. In the default mode, as shown in Figure 2, MSB is located in the data output serialThe first one in the stream. However, this can be reversed so that LSB is the first in the serial stream of data output.

Eight digital output test mode options can be started through SPI. This function is very useful when verifying the capture and timing of the receiver. For the available output position sorting option, see Table 9. Some test modes have two continuous words, which can be alternated in various ways according to the selected test mode. It should be noted that some modes do not meet the data format selection options. In addition, you can allocate custom user -defined test mode in 0x19, 0x1a, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, and 0x20 register address.

PN sequence short mode generates the pseudo -random ratio sequence every 2 1 or 511 bites.

The PN sequence length mode generates a pseudo -random ratio sequence, repeated once every 2 1 or 8388607.

Information about how to change these additional digital output timing characteristics through SPI, see the memory mapping part.

Digital output bruises and error correction codes

Data from AD9239 are sent with 64 -bit data packets serial. These numbers come from the necessity of the output data stream of 16 × encoding clock. The packet includes the header, data and error correction codes (that is, the 8 -bit header+48 -bit data (4 conversion)+8 -bit ECC 64 -bit). The 12 -bit protocol is shown in Figure 2 and Table 1.

Error Code

Error Code (ECC) is an easy -to -implement Hanyu code. During the transmission process, ECC uses seven to correct one error or detects one or two errors.

ECC's MSB is always 0, not for detecting errors. ECC's six LSBs are the different orientations of positioning (see Figure 68 to 75). These bit allows any puppet verification of any bit in the header and data fields.

After calculating the Hamming Strange Puppet test, the seventh puppet school test was applied to the entire group. This puppet verification allows correcting errors in data or ECC bits.

In general implementation, the puppet school test is located in the two positions, but it is extracted from these positions and placed at the end of the packet. Figure 68 to FIG. 75 shows which header and data bit is associated with the puppet school inspection.

In the receiver, perform these strange puppets to check and calculate the receiver's coupling post. The difference between the receiving coupling school inspection and the calculation of the coupling school inspection indicates which bit is wrong.

Drivers

There are three disturbers on AD9239. The disturber is the Ethernet interference frequency (X58+X39+1), the SONET disturber (X7+X6+1), and the static inverter disturber (setting positioning in the groupReverse bit). The disturbers are used to help the number of 1 and 0 in the balance package.

Ethernet and SONET biasers add disturbances to the entire packet (64 -bit), header and data (56 -bit) or only data (48 -bit). The disturburizer is synchronized at the unreasonable terminal or the receiver, and no additional synchronization bit is required. To obtain a copy of the Ethernet or SONET disturbance code, send an email to a high -speed inverter@模 网. Figure 65 and Figure 66 show the serial implementation of the Ethernet and SONET addter. Parallel implementation allows the interoperator and the interpreter to run at a lower clock rate, and can be implemented in the structure of the receiver.

The serial implementation of the Ethernet and SONET bruises is easier to display what is doing. The parallel implementation must be derived from serialized. The final product depends on how much places need to be processed in parallel. For the disturbing device, 64 bits are processed even in the absence of 56 -bit and 48 -bit. In order to achieve this on 56 -bit and 48 -bit, part of the two samples is used to fill the rest of the input word.

Example of the inverter balance

The inverter implements the pre -determined position position to balance the excess range conditions in the converter (all 1 or all 0). In all cases, it will reverse, not just the situation of the overrun.

The disturbing device can be selected based on the number of users of the user. In the anti -phase -based disturbancer, the packet is balanced based on ultra -range conditions. If each packet is balanced, it should be balanced than the special stream. Instead of a random sequence to one package to another, some reversal is set in the predetermined bit position in the bag. This allows the decoding to complete at the receiving end. FIG. 67 shows the reflector in the data packet and the order of the anti -phase device in the header.

Table 11 shows the average data packet in various cases.

If the analog signal exceeds the range, the positive value of the excess range and the negative value beyond the range should be roughly the same. The average value of no disturbance and only increase data is roughly the same. If the header is used to indicate the excess range, the balance in 12 bits will be improved.

Calculating Hangming's Occupation Pigram test

The definition of Hanming Bit is as follows. The definition of a 12 -bit example is given in the figure. Hanying's coupling school inspection is intertwined in the data. This can be easier to see digital relationships. The decoding of the receiving end is just reversing. Another file will illustrate how to correctly correct the errors in the transmission.

P8 digits (MSB of the Puppet School test) is always 0. The P7 digits are the puppet test of the entire data packet after calculating other unprecedented school inspection.

Temperature output pins

The foot can be used as a process temperature sensor to monitor the internal mold temperature of the device. The typical output of this pin is 734 millivoltage, the clock frequency is 250 milliseconds/second, and the negative temperature lift coefficient is 1.12 millivolta/degrees Celsius. The voltage response of the pin is shown in Figure 76.

RBIAS pin To set the internal core bias current of ADC, place a resistor (nominal equal 10.0 kΩ). The resistance current is exported on the chip, and the ADC AVDD current is set to 250 MSPS. The nominal 725 ma. Therefore, 1%or smaller tolerances must be used on this resistor to obtain consistent performance.

VCMX pins

With the external drive voltage of VIN X, you can provide a reference voltage for the external input+V of VIN X. These pins may be needed when connecting external devices (such as amplifiers or transformers) and analog input interfaces.

Rebate pin

Set all SPI registers to its default values and data paths. Using this pin requires the user re -synchronized the digital output. The pin allows only 1.8 V voltage.

PDWN pins

When asserting to be high -electricity, the PDWN pin closes all ADC channels, including output drives. This function can be changed to spare function. See the register 8 in Table 14. Using this function, users can place all channels in the standby mode. The output drive sends a pseudo -random data until the output is disabled by using the register 14.

By asserting that the PDWN pin is high, AD9239 is placed in the power -off mode to close the reference, reference buffer, PLL and bias network. In this state, ADC usually consumes 3MW. If any SPI feature is changed before the power off function is enabled, the chip is continued to work after PDWN is pulled down without resetting. When the PDWN pin is low, the AD9239 returns the normal working mode. The pin allows only 1.8 V voltage.

SDO pin

SDO pin is used to apply the application of 4 -line SPI mode operation. To work normally, it should be connected to AGND through a 10 kΩ resistor. Alternatively, the device pins can be kept open, and the 345Ω internal drop -down resistor pulls the pin. This pin only conforms to 1.8 V logic.

SDI/SDIO pins

SDI/SDIO pins are used for applications that require 4 or 3 -line SPI mode operations. To work normally, it should be connected to AGND through a 10 kΩ resistor. Alternatively, the device pin can be kept open, and the 30kΩ internal drop -down resistance will pull the pin. The pin allows only 1.8 V voltage.

SCLK pin

For normal operation, the SCLK pin should be connected to Agnd through a 10 kΩ resistor. Alternatively, the device pins can be kept open, and the 30kΩ internal drop -down resistor pulls the pins low. The pin allows only 1.8 V voltage.

CSB pin

When working normally, the CSB pin should be connected to AVDD through a 10 kΩ resistor. Alternatively, the device pin can be kept open, and the 26kΩ internal pull -up resistance will pull the pin. By binding the CSB pin to AVDD, all SCLK and SDI/SDIO information will be ignored. In contrast, by binding the CSB pin, all information on the SDO and SDI/SDIO pins are written into the device. This feature allows users to reduce the number of equipment when necessary. The pin allows only 1.8 V voltage.

PGMX pin

By default, all PGMX tube feet are automatically initialized to synchronize pipes. These pins are used to lock FPGA timing and data capture during the initial startup period. These pins correspond to each channel (pgm3 channel A). The synchronous tube's foot should be pulled down until the pin receives the high signal input from the receiver. During this period, ADC outputs a training word. The training word defaults to the value implemented in register 19 to register 20. When the receiver finds the frame border boundary, the synchronous identification is lifted and assertive as a high level, and ADC outputs valid data on the next group boundary.

Once the device has a steady -state operation