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2022-09-24 17:55:53
CD4522BM PDF file CD4522BM Specification Information
Item model number: CD4522BM
Features:
Internally synchronous for high internal and_external speeds
Logic edge-clocked design — increments on positive Clock transition or on negative Clock inhibit transition.
100%_tested for quiescent current at 20-V
5-V, 10-V, and_15-V parametric ratings
Standard symmetrical output characteristics
Maximum input current of 1 μA at 18 V over full package-temperature range;_100 nA at 18 V and_25°C
Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
Applications:
Frequency synthesizers
Phase-locked loops
Programmable down counters
Programmable frequency dividers
NOT RECOMMENDED FOR NEW DESIGNS
describe:
CD4522B programmable BCD counter has a decoded 0 state output for divide-by-N applications. In single stage operation the 0 output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.
The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and_NSR suffixes), and_16-lead thin shrink small-outline packages (PW and_PWR suffixes).