The IC voltage of the working power supply is 5V

12V to the 12V bus

up to 1.3A grid current capacity

TTL compatible 5 digits of programming

output符合VRM 8.5：

1.050V至1.825V，二进制0.025V

台阶

电压模式PWM控制

输出精度高：±1%[ 123]

Overline and temperature

Change

Quick load transient response:

from 0%to 100%duty cycle

Power supply Good output voltage

Overvoltage protection and

Monitor

Realize over current protection

Use MOSFET's RDSON

200KHz internally Oscillator

External adjustable oscillator

from 50kHz to 1MHz

Soft start and inhibitory function

Advanced power supply

Advanced power supply

123]

Core for microprocessor

distributed power supply

Instructions

This device is a power controller aim to provide high -performance high -performance microprocessors to high -current microprocessors DC/DC CON version. The accurate 5 -digit modular converter (DAC) allows the adjustment of the output voltage from 1.050 to 1.825, and the double -order jump is 25mV. High -precision internal bases ensure that the selected output voltage is within ± 1%. The current door -driven door of the peak provides an external power MOS that provides a low -opening loss loss. The device guarantees the rapid protection of the current and overvoltage of the load. In the following cases, the external SCR trigger the pry open input power and the hard overvoltage. As long as the voltage is detected, an internal pry rod is also provided to open the low side MOSFET. If the current is detected, the soft -ranging capacitor is discharged in the system in the hiccup mode.

Electric characteristics (VCC 12V; t 25 ° C, unless there are other regulations)

]

Device description

This device is an integrated circuit implemented by BCD technology. It provides a complete control logic and protection optimizing microprocessor power supply for high-performance antihypertensive DC-DC converters. It is designed to drive N -channel MOSFET in the synchronous rectification buck topology. The device is working normally. The VCC range starts from 5V to 12V, and starts to adjust the output voltage from 1.26V power -level power supply voltage (VIN). The output voltage of this converter can be accurately adjusted, throughThe programming VID pin, from 1.050V to 1.825V, uses 25MV two to advance, and the maximum tolerance of temperature and wire voltage changes is ± 1%. This device provides a voltage mode control of fast transient response. It includes a 200kHz self -excitement oscillator from 50kHz to 1MHz. The error amplifier has a 15MHz gain bandwidth product and the 10V/MS conversion rate, allowing the fast transient performance of the high converter bandwidth. The generated PWM duty cycle range from 0%to 100%. This device prevents over -current from entering the fault mode. This device monitors the current by using the upper MOSFET RDS (ON), which does not require a current fluid resistor. This device provides SO20 packaging.

oscillator

The switching frequency is fixed to 200kHz internally. The internal oscillator produces triangular waveforms to PWM charging and discharge and constant current capacitors. The current is usually 50 μA (FSW 200kHz), which can be connected to the RT pin and GND or VCC. Because the RT pin is maintained at a fixed voltage (typical. 1.235V), the frequency variable and the current sinks down (forced). In particular, the frequency connected to the GND increase (current from the pins), according to the following relationship:

When connecting the RT to VCC 12V or VCC 5V Reduce (the current is forced into the pins), according to the relationship with the following:

The relationship between the switching frequency and the RT is shown in Figure 1.

Note that this is because the input current did not enter a tube foot, so the input current oscillator is not stopped to a tube foot.

digital mode converter

The built -in digital mode converter allows the output voltage from 1.050V to 1.825V25 mm. Show in Table 1. Internal reference is trimmed to ensure accuracy of 1%.

Internal reference voltage adjusted by voltage recognition (VID) pin programming. These are the internal DAC TTL compatible inputs, which are implemented through a series of resistors that provide internal reference voltage. VID code drives multi -road reusopter, the multi -road repeat device is at the point of the separation line. The DAC output is transmitted to the amplifier that obtains the Vprog reference voltage (that is, the setting value of the error amplifier). Provide internal pulling (achieved through a 5μA current generator); in this case, the programming logic 1 is enough to let the pins float, and the programming logic 0 is short enough to pins.

Voltage recognition (VID) pin configuration also sets good power threshold (PGOOD) and overvoltage protection (OVP) threshold.

Soft start and inhibitory

When starting, to the external capacitor CS through 10 μA constant currentS is charged and generated slope, as shown in Figure 2. When the voltage on the soft startup capacitor (VSS) reaches 0.5V, the low -power MOS is turned on and the output capacitor discharges. When the VSS reaches 1V (the lower limit of the oscillator triangle wave), the upper limit MOS starts the switch and the output voltage begins to increase. The VSS growth voltage initially cut the output of the error amplifier, so VOUT linear increased, as shown in Figure 2. At this stage, the system works in a loop. When VSS is equal to VCOMP, release the clamp of the error amplifier output end. In any case, the error amplifier is maintained, allowing VOUT to increase at a lower slope (ie, the slope of the VSS voltage, see Figure 2). In the second stage, the system works in a closed loop, and the reference value continues to increase. As the output voltage reaches the expected value VPROG, at the same time, the clamping of the input end of the error amplifier is removed, and the software and hardware are simulated to start. VSS increases until the maximum value is about 4V. If the VCC and OCSET pin exist at the same time, the soft start will not occur, and the short circuit to the ground in the related pin will not exceed their own opening threshold; in this way, the device will start switching only when the two power supply exists at the same time. During the normal operation period, if any underwriting voltage is detected on one of the two power supplies, the SS pin is short -circuited inside the ground, so the SS capacitor is quickly discharged. The device enters the state of suppression, forcing the SS pin to be less than 0.4V. In this case, the two external MOSFETs remain unchanged.

The driver capacity of the driver's room height and low -voltage side drive allows the use of different types of power MOS (can also reduce RDSON) to keep fast switch conversion. The low -voltage side MOS driver is directly provided by VCC, and the high -voltage side drive is provided by the starting pin. Using adaptive dead zone control to prevent cross -conductors and allow multiple types of MOS FETs. When the grille is greater than 200mv, the upper MOS is avoided, and the lower MOS is turned on to avoid if the phase pins exceed 500 millivolta, it should be avoided. In any case, the upper MOS is closed on the low pressure side. At 5V and 12V, the peak currents of high levels (Figure 3) and low levels (Figure 4) are displayed in these measurements. For lower drivers, the source peak current is 1.1a@vcc 12v and 500ma@vcc 5V, while the Sink peak value is 1.3A@vcc 12V, 500ma@vcc 5V. Similarly, for the upper -layer driver, the peak of the source pole is 1.3a@vboot V phase 12V, 600ma@vboot V phase 5V, the peak of the trap is 1.3a@vboot v phase 12V, 550ma@vBOOT V Essence

Figure 3. High -sided driving peak current.

VBOOT V phase 12V (left) VBOOT VPhase 5V (right) CH1 High -voltage side grille CH4 inductance current

Monitoring and protection

output voltage through pins 1 (vSEN) performed (VSEN) monitor. If the value of the ± 10%(typical value) of the programming value is not valuable, the PowerGood output forced is low. When the output voltage reaches more than 17%(typical values), the device provides the one on the nominal nominal of overvoltage protection. If the output voltage exceeds this threshold, the OVP pin is forced to high level (5V) and lower drivers as long as the voltage is detected, and it will open. The OVP pin can provide a current of up to 60 mAh (minutes) to trigger an outer threaded threaded input fuse. When the low -side MOSFET is available, this function does not use SCR, which helps keep the output low. In order to perform current protection, the device compares the voltage drop of the high -voltage side MOS because the voltage of the external resistance (ROCS) is connected to the OCSET pin and the drain. Therefore, over -current threshold (IP) can be calculated through the following relationship:

The typical value of the IOCS is 200 μA.

To calculate the ROCS value, we must consider the maximum RDSON (and change with temperature changes) and the minimum value of IOC. In order to avoid unexpected triggers of overcurrent protection, this relationship must be

Satisfied:

Type u0026#8710; In the case of short -circuited output, the soft startup capacitor discharges with constant current (10 μA typical values), and

S pin reaches the 0.5V soft start phase. During the soft startup process, over -current protection is always activated. If such incidents occur, the device will turn off two MOSFETs, and the SS capacitor will be charged again after reaching the upper limit of about 4V. The system now works in interrupt mode, as shown in Figure 5A. After eliminating the reasons for overcurrent, the device works normally without a power switch.

The inductor design

The inductor value is defined by the discount between the transient response time, efficiency and cost. The inductor must be calculated to maintain the output and maintain the input voltage change ripple current u0026#8710; IL between 20%and 30%of the maximum output current. The inductance value can be calculated through the following relationship:

Among them, the FSW is the switch frequency, VIN is the input voltage, and VOUT is the output voltage. Figure 5B shows the ratio of the output voltage of different electrical induction values u200bu200bwhen VIN 5V and Vin 12V. Increasing the electrical value will reduce the ripple current, but it will also reduce the transient response time of the converter load. If compensated network settingsIn good calculation, the device can open or close the duty ratio up to 100%or drop to 0%. The response time is now the time required to change its current value from the initial value to the final value. Since the inductor has not completed the charging time, the output current is provided by the output capacitor. The shorter the response time, the smaller the output capacitance. The response time of the load transient state is different due to the application or removal of the load: if the load is applied, the inductor is equivalent to the voltage charging voltage between the input and output. During the disassembly process, it only discharge from the output voltage. The following expression gives the compensation network response fast enough u0026#8710; i load transient approximate response time:

The worst situation depends on the available situation depends Input voltage and selected output voltage. In any case, the worst case is the response time after the load removal, the minimum output voltage is programmed, and the maximum input voltage is available.

Output capacitor

Since the microprocessor requires a current change of more than 10A when the microprocessor is undergoing a load, the output capacitor is the basic component of the rapid response of the power supply. In fact, in the first few micro seconds, they provide current to the load. The controller immediately identifies the load transient and sets the duty cycle to 100%, but the current slope is limited by the inductor value. Due to the current changes inside the capacitor (ignore ESL): u0026#8710; vout u0026#8710; IOUT · ESR

The capacitor needs to maintain the minimum current value without load. The voltage caused by the discharge of this output capacitor can be concluded through the following formulas:

Among them, DMAX is the maximum duty cycle, that is, 100%. The lower the ESR, the lower the output. The lower the static ripple of the output voltage during the transient transient.

Input a capacitor

Input capacitors must withstand the ripple current generated during the upper MOS drive, so it must have a low ESR to minimize the loss. The RMS value of this ripple is:

Among them, D is the duty ratio. When D 0.5, the equation reaches the maximum value. The losses in the worst case are:

Compensation network design

The voltage reduction control function shown in FIG. 7 The size and cost of the output capacitor. This method restores the part of the voltage drop caused by the output capacitor ESR in the load transient, and the dependence of the output voltage to the load current is introduced: under the light load, the output voltage will be higher than the nominal level, and at high loads at high loads, at high loads Below, the output voltage will be lower than the nominal value.

As shown in Figure 6, the ESR drops in any case, but the use of the speed reduction function will have the smallest output voltage. In fact, the introduction and output current introduced and output currentProperly static error (VDROOP in Figure 6). Because there is no sensor resistance, the inherent resistance of the inductance is used (several M u0026#8486;). Therefore, the low -pass filtering inductance voltage (ie, the inductance current) is added to the feedback signal to achieve a drooping function in a simple way.指的是如图7所示，闭环系统的静态特性为：

式中，VPROG是数模转换器的输出电压（即设定值）， RL is an inductive resistance. The second item of the equation allows positive offset under zero load (u0026#8710; v+); the third item is introduced to the drooping effect (u0026#8710; vdroop). Note that if the following situation occurs, the drooping effect is equal to ESR drop:

Considering the previous relationship, you can determine R2, R3, R8 and R9 As follows: Select a value within the range of hundreds of K u0026#8486; to obtain another actual value component

According to the above equation, it is obtained:

Among them IMAX It is the maximum output current.

It must be selected to obtain R3 u0026 LT; u0026 LT; R8 // R9 to allow these and continuous simplification. Therefore, under the speed reduction function, the output voltage decreases as the load current increases, so DC output impedance is equal to the resistance path. When the output impedance and frequency are constant, it is easy to verify that the output voltage deviation of the load transmission is minimal. In order to choose other components of the compensation network, the transmission function of the voltage ring was considered. In order to simplify the analysis, assuming R3 u0026 LT; u0026 LT; RD, where RD (R8 // R9).

You can ignore the connection between the R8 and phase to calculate the transmission function, because as it will be seen later, this connection is only important at low frequency. So R4 is considered to be related to VOUT. With this consumption, the voltage circuit has the following transmission functions:

Note: In order to understand the reason for the previous assumptions, the scheme in Figure 9 must be considered. In this scheme, because the electromot current is instead of the drooping function within the frequency range, these currents are basically the same for the drooping function, and it is assumed that the drooping network does not represent the electrical sensor charging.

Because of the scope of interest | Gloop | u0026 gt; u0026 gt; 1.

In order to get a flat shape, the considering relationship will naturally follow. The VRM demonstration board description Figure 10 shows the circuit principle diagram of the VRM assessment board. The design provides up to 28.5A for the 8.5 flexible motherboard application developed by VRM. A additional circuit induction to a VTT bus (1.2V typical value), and in the following cases, a 2.5ms (Typical value) Delayed VTT_PWRGD signal this orbit voltage exceeds 1.1V. The assertion of the VTT PWRGD signal enables the device with Enout input.

Efficiency

Under different output voltage, the relationship between the measurement efficiency and load current is shown in Figure 11. Two MOSFET STS12NF30L (30V, 8.5m u0026#8486;, VGS 12V) in the application of high -voltage side connection in the application, and three of which are used for the low side.

inductor design

Since the maximum output current is 28.5A, for 20%ripple (5A), the selected inductor is 1.5μH Essence Output capacitors

In the demonstration, 6 OSCON capacitors with 6sp680m are used, and the maximum ESR of each capacitor is equal to 12m u0026#8486; Therefore, the ESR generated is 2m u0026#8486;. For the worst case of 28.5A load transient, the voltage drops to: u0026#8710; vout 28.5*0.002 57mv Considering the maximum load current, the voltage drop caused by capacitor discharge during the load transient process is 100%, and the result is the result. 46.5mv, the programming output is 1.85V.

Input capacitors

For iOUT 28.5A and D 0.5 (the worst case of input current ripples), IRMS is equal to 17.8A. The Oscon Elec TrolityC container 6SP680M, which is equal to the three maximum ESRs is equal to 12m u0026#8486; to compensate the ripple. Therefore, the losses in the worst case are:

Over current protection

Use the relationship reported in the relevant chapter to replace the demonstration board parameters, (IOCSMIN 170μA; IP 33A; rdsonmax 3m u0026#8486;), as a result, Rocs 1K u0026#8486;.