Features

2.7V to 5.5V power operation

50MHz serial interface

10MHz multiplier bandwidth [ 123]

#8226: ± 15V Reference Input

Low fault energy: 5nv-s

extended temperature range: -40 ° C to++ 125 ° C

10 Director MSOP Pack

12 digits of monotonous

Power -out -of -the -agencies of electricity detection

Chrysanthemum chain mode

Receiving function

industry standards Point configuration

Application

Portable battery power supply instrument

123]

programmable amplifier and attenuator

Digital control calibration

] Composite video

Ultrasonic

DAC7811

is a CMOS, 12 -bit, current output digital mode converting conversion Device (DAC). The working voltage of the device is from 2.7V to 5.5V, suitable for battery power supply and many other applications.

This DAC uses a dual -buffer 3 -line serial interface that is compatible with SPI #8482;, QSPI #8482;, Microwire #8482;, and most DSP interface standards. In addition, when multiple devices are used, the serial data output pin (SDO) allows the chrysanthemum chain. Data Reading allows users to read DAC registers through SDO pin. When power is powered, the internal displacement registers and locks are filled in zero, and the DAC output is at zero scale.

DAC7811 has excellent 4 -quadrant multiplication, and has a large signal multiplier bandwidth of 10MHz. The exerted external reference input voltage (VREF) determines the full marking output current. When integrated feedback resistors (RFB) provide temperature tracking and full -standard voltage output, the external current voltage precision amplifier is combined.

DAC7811 uses 10 lead MSOP packaging.

Typical features: vdd +5V

When TA +25 ° C, unless there is another explanation.

Typical features: vdd +2.7V

ta ++ At 25 ° C, unless otherwise explained.

Operation Theory

DAC7811 is a single channel, current output, 12 -digit mode converter (DAC). The structure of the architecture, as shown in Figure 25, is a R-2R trapezoidal configuration, which has three MSB segments. Each 2R leg of the trapezoidal chart is either switched to iOUT1 or IOUT2 terminals. DAC's iOUT1 terminal is kept at a virtual GND potential by using an external I/V converter. The R-2R trapezoid diagram is connected to the external reference input VREF that determines the DAC full-scale current. The external reference of the R-2R trapezoid to 10K ± 20%provides load impedance that is not related to the code. The external reference voltage can be changed in the range of -15V to+15V, thereby providing a bipolar input current operation. By using an external I/V converter and a DAC7811 RFB resistor, the output voltage range from -vref to VREF can be generated.

当使用外部I/V转换器和DAC7811 RFB电阻器时，DAC输出电压由方程式1给出：[123 ]

Determine the position or code of each leg. Because the DAC output impedance of the IOUT1 terminal changes with the change of the code, the noise gain of the external I/V converter will also change. Therefore, an external I/V converter operational amplifier must have a sufficiently low offset voltage, so that the amplifier's offset is not modified by changing the DAC IOUT1 terminal impedance. Compared with the DAC code, an external operational amplifier with a large offset voltage will generate an INL error in the DAC7811 transmission function.

In order to obtain the best linear performance of DAC7811, it is recommended to use a low offset voltage amplifier (such as OPA277) (see Figure 26). The circuit allows VREF to swing from -10V to+10V.

(1), ↓ - negative logic conversion, default CLK mode; ↑+positive logic conversion; x do not care.

Serial interface

DAC7811 with 3 -line serial interface (SYNC, SCLK and SDIN), SPI, QSPI and microfinance standards, and most digital signal processor (DSP) devices (DSP) devices (DSP) devices (DSP) devices (DSP) devices compatible. For examples of typical writing sequence, please refer to the sequential drawing of serial writing operation(Figure 28). The writing sequence starts from the low level of the synchronous line. The data from the DIN line was sent to the 16 -bit displacement register by the clock to the SCLK. The serial clock frequency can be as high as 50MHz, which makes DAC7811 compatible with high -speed DSP. SDIN and SCLK input buffers are closed when synchronized, which will minimize the power consumption of the digital interface. After the synchronization becomes lower, the digital interface will respond to the SDIN and SCLK input signals, and the data can now be transferred to the device. If there is a non -active clock edge before the synchronization becomes lower, but it will ignore it before the first active clock edge. If you are using SDO pins, the synchronization must be kept at a low position until the edge of the non -active clock edge after the edge of the 16th activity clock.

Input displacement register

The width of the input shift register is 16 bits, as shown in Figure 27. Four MSB is the control bit C3 – C0; these bits determine which function is the synchronous ascending edge or independent mode in the chrysanthemum chain mode. The remaining 12 bits are data bit. In loading and updating commands (C3 -c0 0001), these 12 data bit will be transmitted to the DAC register; otherwise, they will not work.

Synchronous interrupt (independent mode)

In the normal writing sequence, the synchronization line remained at a low level in at least 16 decreases in SCLK, and and of. DAC was updated at the 16th decline. However, if Sync is at a high level before the 16th decline, it will be used as a interrupt of the sequence. The displacement register is reset, and the writing sequence is considered invalid. The update of the DAC register content and changes in the operation mode will not occur.

Chrysanthemum chain

DAC7811 is powered by the chrysanthemum chain mode. When two or more devices are connected in series, the chrysanthemum chain mode must be used. When the SDO output of the first device is connected to the SDIN input of the next device, the SCLK and Sync signals are shared on all devices, and so on. In this configuration, each DAC7811 in the chain requires 16 SCLK cycles. Please refer to the timing map of FIG. 28.

For N devices in the chrysanthemum chain configuration, the 16N SCLK cycle is required to move the entire input data stream. After receiving the SCLK edge of the 16N activity after the decline synchronization, the data flow becomes complete. Synchronization can increase to high levels to update N devices at the same time.

When the synchronization is raised, each device will execute the function defined by four DAC control bits C3-C0 in its input displacement register. For example, the C3-C0 of each DAC that is updated in the chain must be 0001, and the C3-C0 of each DAC in the chain that remains unchanged must be 0000.

When the synchronization signal is kept low, you can first send a company that contains exact SCLK cyclesContinue flow, and then improve synchronization later. Nothing happens before the synchronous ascending edge, and then each DAC7811 in the chain will execute the function defined by four DAC control bits C3-C0 in its input displacement register.

Control bit C3 to C0

Control bit C3 to C0 allows various functions of control DAC; see Table 2. The default settings when DAC is powered on: When the clock drops, the data clock enters the displacement register; the chrysanthemum chain mode is enabled. When the device is powered on, the zero scale is loaded to the DAC register and iOUT line. The DAC control bit allows users to adjust certain features as part of the initial sequence; for example, the chrysanthemum chain may be disabled without use, the edge of the activity clock can be changed to the rising edge, and the DAC output can be cleared to zero or medium. Scale. Users can also initiate the recovery of DAC register content for verification.

Application information

Stable circuit

For current-voltage design (see Figure 29), DAC7811 current output (IOUT) and and and and with The connection of the computing amplifier inverter node should be as short as possible and meets the correct printing circuit board (PCB) layout design practice. There is a step function for each code change. If the gain bandwidth (GBP) of the operation amplifier is limited and the parasitic capacitance of the reverse node is too large, the peak of gain is possible. Therefore, for the stability of the circuit, the compensation capacitor C1 (1PF to 5PF, typical value) can be added to the design, as shown in Figure 29.

The amplifier selection

For the multiplication digital mode converter (MDAC), there are many options and many differences in the appropriate calculation amplifier. It is a key aspect to use MDAC to generate analog signal. However, there are other issues that need to be considered, such as amplifier noise, input bias current, bias voltage, and MDAC resolution and fault energy. Table 3 and 4 gives some operational amplifiers suitable for low power consumption, fast and stable and high -speed applications.

Positive voltage output circuit

As shown in Figure 30, in order to generate a positive voltage output, the negative reference is input to DAC7811. Due to resistance errors, this design is recommended instead of using reverse amplifiers to reverse the output. For negative reference, the VOUT and GND levels of the reference voltage are moved to virtual grounding, and the DAC7811 is provided to DAC7811 through the computing amplifier.

Dual output section

DAC7811 as a 2 -quadrant multiplication DAC, which can be used to generate single -pole output. The polarity and VREF of the full marked extent output iOUTThe input reference voltage is the opposite. Some applications require a complete 4 -quadrant capacity or bipolar output swing. As shown in Figure 31, the external operational amplifier U3 is added as a demand and amplifier. Its gain is 2X and expands the output range to 5V. By using the 2.5V of the 2.5V of the reference voltage offset U3, the 4 -quadrant multiplication circuit is achieved. According to the circuit transmission equation given in Formula 2, the output voltage generated from the input data (d) from the code 0 to the full marker is vout - 2.5V to the VOUT +2.5V.

Outblowing loss is an important error in Figure 31.

The programmable current source circuit

DAC7811 can be integrated into the circuit in FIG. -Stage conversion. The circuit has two -way current and high voltage compliance. For the matching resistance network, the load current of the circuit is shown in the formula 3:

The value of R3 in the formula 3 can reduce the output current drive of U3. U3 can drive ± 20mA in two directions, and the voltage compliance is limited to 15V by the U3 power supply. According to Formula 4, it is not recommended to eliminate the circuit compensation capacitor in the circuit C1:

as the output impedance ZO changes. , ZO is infinite, and the circuit is most suitable for current source. However, if you use an unheard of resistance, ZO is positive or negative, and negative output impedance is the potential cause of oscillation. Therefore, by merging C1 to the circuit, possible oscillation problems can be eliminated. For key applications, you can determine the value of C1; but for most applications, it is recommended to use the value of several PF.

Cross reference

DAC7811 has an industry standard pin. Table 5 provides cross -reference information.