ATO25D1GA-10ED: FLASH memory. Company advantage inventory.

feature

generally

Serial Peripheral Interface

? Mode 0 and Mode 3

Standard, Quad SPI

?Standard SPI: SCLK, CS#, SI, SO

?Quad SPI: SCLK, CS#, SIO0, SIO1,

SIO2/W#, SIO3/Hold# Single Supply Operation

?Full voltage range: 2.7V to 3.6V read, erase

and program operation

organize

? Memory cell array: (128M + 4M) x bytes

Data register: (2048 + 64) x bytes

Automatic programming and erasing

? Page Program: (2048 + 64) x bytes ? Block Erase: (128K + 4K) x bytes =

64 pages

page read operation

?page size: (2048 + 64) bytes

?page read (cell array to page buffer):

25us (max)

?Serial page access: 104MHz,

133MHz (CL = 15pF)

fast write cycle

?Programming time: 200us (Typ.)

? Block erase time: 2ms (Typ.)

Electronic identification

? JEDEC standard 1-byte manufacturer ID and 1-byte device ID.

Write-back program operation

? No external fast page copying required

buffer

security function

?OTP area, 16K bytes (8 pages)

?

hardware data protection

? Program/Erase is locked during power-up

transition. ?W# pin with

Status Register Bit Protection

the specified storage area. state

Register Block Protection Bits (BP2,

BP1, BP0) configuration in the status register

Part of the memory is read-only

data integrity

?Endurance: 100K program/erase

number of cycles

Data retention period: 10 years

error management

?Internal ECC code generation

?1bit/528bytes ECC, 1NOP/528bytes

Bag

?8 pieces of 8x6 WSON

?16-pin SOIC 300 million

General Instructions

ATO25D1GA is 1Gbit with 32Mbit spare capacity. The device operates from a 3.3V supply

supply. Its NAND cells provide the most cost-effective solution for solid-state mass storage

market. The memory is divided into blocks that can be erased independently, so it is possible to

Retain valid data while deleting old data. The device contains 1024 blocks, consisting of

64 pages, consisting of two NAND structures of 32 flash memory cells connected in series. a program

Operations can be performed on a typical 200us of 2048 bytes, and erase operations can be performed.

Executes in a typical time of 2ms on 128Kbyte blocks. The data in the page can be read out in 25ns

Cycle time per byte. On-chip write control automates all program and erase functions

Includes pulse repetition if necessary and internal verification and data margins. even

Write-intensive systems can take advantage of the extended reliability of the ATO25D1GA

100K program/erase cycles by providing ECC (Error Correcting Code) in real time

mapping algorithm.

?ATO25D1GA has serial peripheral interface and software protocol to allow operation

Operates on a simple 3-wire bus when in single I/O mode. These three signals are the clock input (SCLK),

Serial Data In (SI) and Serial Data Out (SO). Enable serial access to the device by

CS# input. When in the four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin

Become the SIO0 pin, SIO1 pin, SIO2 pin, SIO3 pin for address/virtual bit input and data output.

The copy function can optimize defective block management:

Program operation fails, data can be programmed directly in another page of the same page

Array part without the time-consuming serial data insertion stage. ATO25D1GA is

Large non-volatile storage applications such as solid-state file storage and

Other portable applications requiring non-volatile.

?Automatic program/erase algorithm after issuing program/erase command

Program/erase and confirm that the specified page or sector/block location will be performed. depending on

2 KB can be programmed at a time. Pages can be erased in erase groups of 128KB. to

Provides a convenient interface for the user, including a status register to indicate the user's status

chip. Status read commands can be issued to detect the completion status of the program or

The erase operation is performed through the OIP bit. Advanced security features enhance protection and safety features