Features

3.3V logic interface TTL logic level input

Intelligent logic for power -powered/hot insertion state control

[[

123] Improved switch DV/DT antipitrus degree is 500 V/

single -chip integrated circuit reliability

Low -match Ron [ 123]

Eliminating the need for zero cross switch

flexible switch to fixed, you can transition from the ringtone mode to the free/call mode.

Clean, bouncing switch

level three -level protection, including integrated flow limit, voltage clamping and SLIC protection heat shutdown

5V operation, power consumption lt; 10 mw

smart battery monitor

]

16 -needle small SOIC

Application

voip gateway

123] Digital Ring Road Carrier (DLC)

pbx system

Digital adding main line (DAML)

#8226 ; Hybrid fiber coaxial cable (HFC)

Fiber in the ring (Fitl)

Bank

Description

CPC7591

is a member of the next -generation line card access switch (LCAS) series of the Ixys Integrated circuit department. This single -piece four -polar solid switch is encapsulated by 16 -shot SOIC. It provides necessary functions to replace the 2-Form-C electrical ringing relay and its related buffer circuits on the 2-Form-C electrical ringing relay and its related buffer circuits on the traditional simulation line card or modern integrated voice and data (IVD). These line cards are located in the Central Office (CO) , Access and PBX devices. Because the device contains the disconnection of cutting -edge and ring lines and a solid switch for bell injection/return, it only needs +5 V power to operate, and the TTL logic level input for control is required. CPC7591 provides stable start -up adjustments in systematic power -power and heat -insertion applications. Once activated, enter the traditional TTL logic level that responds to the traditional TTL logic level, so that the CPC7591 can be used with the logic of only 3.3V.

For negative transient voltageProtection, CPC7591BA version includes SCR providing voltage folding protection for SLIC and subsequent circuits, while the CPC7591BB version uses clamp diode to VBAT pin. For positive transient voltage protection, all versions provide clamp diode for FGND pins.

订购信息

图1：CPC7591方框图

功能描述

[123 ] Introduction

CPC7591 has three states:

Talk: Broken switch SW1 and SW2 closed, the bell switch SW3 and SW4 open.

ringtone: The bell switch SW3 and SW4 are closed, and the disconnect switch SW1 and SW2 open.

All off: All switches are turned on.

CPC7591 uses simple TTL -level logic input control to provide the function of first break, then, and then break, and switch from bell to the call status. The solid switch structure means that pulse noise will not produce during the switch during the bell or bell, thereby eliminating the needs of the external zero -cross switch circuit. The state control is input through the TTL logic level, so there is no additional driving circuit. Linear disconnection switch SW1 and SW2 have very low RON and excellent matching features. The smallest opening of the SW4 at+25 ° C touches the cross -clicking voltage of 465 V, which has sufficient protection to prevent a hit when the transient failure (ie, transmitting the transmitted transmission to the bell generator) occurs). Put on.

CPC7591 integrates over -voltage clamp circuits, source of flow restrictions and thermal check mechanisms, and provides protection for SLIC under failure. Positive and negative thunderbolt poured currents have reduced the overflow circuit, and the dangerous potential is transferred from SLIC by protecting the diode bridge or optional integrated protection SCR. The current limit and the heat shutdown circuit also reduces the power crossing potential.

In order to protect the effect of CPC7591 exempt from voltage failure conditions, auxiliary protectors need to be used. The secondary protector must limit the voltage at the TLINE and RLINE terminals to the level below the maximum breakdown voltage of the switch. In order to minimize the stress on the solid -state contact, it is strongly recommended to use a folding or pry rod -type secondary protector. After the correct selection of the secondary protector, using the CPC7591 line card will meet all related ITUs, LSSGR, TIA/EIA, and IEC protection requirements.

CPC7591 works only through a +5 V power supply. This makes the device have extremely low idling and power consumption in almost any battery voltage range. The battery voltage used by CPC7591 has dual function. For the purpose of protection, it is used as a fault circuit source source for internal integrated protection circuits. Secondly,It is used as a reference so that CPC7591 will enter the full level when the battery voltage loss is lost.

IOU -voltage switching circuit

Introduction

Intelligent logic in CPC7591 now provides switching status control during power supply and power -off conversion. The internal detector is used to evaluate the VDD power supply to determine when the VDD rising voltage switch locks the lock -up circuit, and when to use the decreased VDD to determine the lack of the underwriting switch locking circuit. At any time, as long as there is a low -VDD condition that is not satisfactory, the locking circuit will cover the user switch control by blocking the information on the external input pin and adjusting the internal switch command to the full level status. After the VDD recovery, the switch will be kept in the state until the lock input is pulled down.

The rising VDD switch locking the release threshold is set internally to ensure that all internal logic is correct and normal before receiving the external switching command from the input to control the switch state. For the decreased VDD event, the locking threshold is set to ensure that the time when the switch is forcibly closed and the external input is suppressed, and the logic and switching behavior are normal.

In order to facilitate the control of the heat insertion and the system, the insertion has an integrated weak upper pull resistor to the VDD power rail. This resistor keeps non -drive insertion sales in a logical high level state. This allows the circuit board designer to use CPC7591 with FPGA and other devices that provide high impedance output during power -power and logical configuration. When the system's lock control driver has a low -minimum absorption capacity of 4mA, the weakly pulling fan output is up to 32.

Precautions for the design of heat plug -in and power -on circuits

Six possible startups may occur during power -on. They are:

1. All inputs defined when power -powered and 闩 闩 0

2. All inputs defined when power -powered and 闩 lock 1 All inputs defined when 闩 lock z

4. All inputs

5. When the power -power and 闩 lock 1 ]

6. All inputs are not defined when the power supply and 闩 lock z

In all the startups listed above, the CPC7591 will keep all its switches in a full disconnection during power. When the VDD requires meetings, LCA will complete its startup program in one of the three cases.

For startup solution 1, when VDD is valid, CPC7591 will be converted from the state of full level to the state of input definition.

For the launch plan 2, 3, 5, and 6, the CPC7591 will be powered on in full level and keeps it in this state until the lock -up is low. This allows the board to insert the power supply system but not configured the service, or you need to wait for other devices to match firstThe uncertainty of the main board is in full level.

The launching scheme 4 will start when all switches are in the state of customs. Randomly change the state with load. Because under this start -up conditions, the LCAS state after power -on cannot be predicted, this state should not be used.

In the design of the lock pins of the multi -port card alone, multiple (or all) lock pins buses can be used together to create a single -board input and enable control.

Switching logic

Start

CPC7591 Use intelligent logic to monitor the V power supply. When V is lower than the threshold set inside, the intelligent logic will put the control logic in the state. After starting, the internal pull on the lock sales locks the CPC7591 in the whole state until the insertion is pulled down to the low logic. Before asserting the logic of the lock -up office, the switch control input must be adjusted appropriately. Detailed design detailed design

Timing fork timing

CPC7591 When switching from bell tingling state to calling state, it can use simple TTL logic levels to control the bell switch SW3 and SW4 relative to disconnects relative to disconnecting. The release of two available technologies for the release of switch SW1 and SW2 is called first -combination, then break first, and then combined. When the switching contacts of the SW1 and SW2 are closed (closed) before the bell switch contacts of the SW3 and SW4 are closed (closed), this is called first closed and then disconnected. When the ringing contacts of the SW3 and SW4 are disconnected (disconnected) before the switch contacts of SW1 and SW2 are closed (closed), the operation occurs first. In CPC7591, through the appropriate TTL logic level input sequence of the device, it can easily complete the operation of first -pass, then, and then break.

Passing and then break operation

To use the first combination and then break operation, please change the logic input directly from the bell state to the call state. When the break -off switch SW1 and SW2 are closed, the call state is used to open the backbell switch SW3. The bell switch SW4 is kept closed until the ringing current is over zero. When it is in a preconceived state, the bell potential exceeding the CPC7591 protection circuit threshold will be transferred from SLIC. The order of this operation is shown below.

Trends first, then disconnecting bell conversion logic sequence

first break the ringling switch to release the fixed two -way pass through the two -way. T interface execution. As an input, T can disable all CPC7591 switches when pulling the logic. Although logically disabled, an activated (closed) bell switch (SW4) will be closed until the next current is over the spare incident. The order of this operation is shown below.

1. Pull TSD to the lower limit of logic and endRinging state. This will turn on the bell switch (SW3) and prevent any other switch off.

2. Keep the TSD low in half of the ringing cycle, so that there is enough time to occur with zero current events, and the circuit enters the first break and then the state.

3. In the low time of TSD, clear the input of the call status (low logic).

4. Release TSD, allowing the interior to start the interrupted switch.

When using TSD as input, the proposed two states are ""0"