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2022-09-24 20:26:29
UCC28061DR SMD SOP-16 Power Management Function
Power Management The UCC28061DR contains two Pulse Width Modulation (PWM) power converter control circuits. The boost PWM power converter ramps the current in the boost inductor for a period of time proportional to the voltage on the boost error amplifier output. Each power converter then turns off the power MOSFET until the current is boosted on the zero current sense inputs (ZCDA and ZCDB) and the inductance decays to 0. Power management UCC28061DR once the inductor
The current decays to 0 and the power converter begins another cycle. This on/off cycle produces a triangular wave
Current, peak current is set by timing and power input voltage, power management UCC28061DR
The average line current is exactly half the peak line current, power management UCC28061DR
When t and L are substantially constant over the AC line cycle, the resulting triangular current waveform
In each switching cycle, there is an average value proportional to the instantaneous value of the rectified AC line
Voltage. This structure operates at line frequency and a
near-unity power factor.
The outputs of the two PWMs are 180° out of phase, so that the power line ripple current of the two PWMs is
Greatly reduces the ripple current from each individual PWM. This design reduces ripple current at the input
and output, allowing input and output filters to reduce size and cost.
Optimal phase balance occurs if the individual power stages and on-time are well matched. Unmatch
The inductance value does not affect the phase relationship.
The punctuality of the gate drive varies with the output voltage of the error amplifier, KT, as shown in Equation 3.
Location: VCOMP is the output of the error amplifier and 125 mV is the offset of the modulator.
For a smooth transition between two-phase and single-phase operation, KT is doubled for single-phase mode: ?KTLS = 2×KTL; single-phase operation is proactive
The maximum output of the error amplifier is limited to 4.95 V. This value, minus the 125 mV modulator offset, limits the time to Equation 4.
This time limit sets the maximum power that the converter can deliver at a given input voltage level.
The switching frequency of each phase is limited by the minimum period timer. if the current value is in. Decayed to 0 before
The minimum period timer expires, delaying the start-up, resulting in discontinuous phase currents.
Restart timer ensures start in any case, if one of the stages ZCD enters, restarts both stages
does not transition to low for about 200µs. Prevent the circuit from working continuously
Conduction mode (CCM), the restart time is only triggered when the two-phase current is 0.
Under normal operating conditions, the UCC28061 regulates the relative phase of channel A and channel B
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