EP1S40F1508C6: Field Programmable Gate Array

Stratix® devices contain row- and column-based two-dimensional

Architecture that implements custom logic. a series of columns and rows

Interconnects of different lengths and speeds provide signal interconnects

Logic Array Block (LAB), between memory block structure and DSP

piece.

The logic array consists of LABs with 10 logic elements (LEs) in each LAB

LAB. LE is a small part of the logic that can be implemented efficiently

User logic functions. LAB is divided into different rows and columns

equipment.

M512 RAM blocks are simple dual-port memory blocks with 512-bit plus

Parity (576 bits). These modules provide dedicated simple dual port or

Single port memory, up to 318 MHz, up to 18 bits wide. M512 block is

Columns divided across certain LABs for the entire device.

M4K RAM blocks are true dual port memory blocks with 4K bits

Parity (4,608 bits). These modules offer dedicated true dual port, simple

Dual-port or single-port memory, up to 36 bits wide, up to 291 MHz.

The blocks are divided into columns across devices

certain laboratories.

The M-RAM block is a true dual port memory block with 512K bits

Parity (589, 824 bits). These modules provide a dedicated true dual port,

Simple dual-port or single-port memory up to 144 bits wide

269MHz. Several M-RAM blocks placed individually or in pairs

in the logical array of the device.

Digital Signal Processing (DSP) blocks for up to eight

Full-precision 9×9-bit multipliers, four full-precision 18×18-bit multipliers

Multiplier or a full-precision 36x36-bit multiplier with add or add operations

Minus features. These modules also contain 18-bit input shift registers for

Digital signal processing applications, including FIR and infinite pulse

Response (IIR) filter. The DSP block is divided into two columns

equipment.

The I/O pins of each Stratix device are located at

The end of the LAB row and column around the periphery of the device. input Output

Pins support multiple single-ended and differential I/O standards.

Each IOE contains a bidirectional I/O buffer and six registers for

Record input, output and output enable signals. when with

dedicated clocks, these registers provide excellent performance and

Interface support with external storage devices such as DDR SDRAM

FCRAM, ZBT and QDR SRAM devices.

High-speed serial interface channel supports transfers up to 840 Mbps

I/O using LVDS, LVPECL, 3.3V PCML or HyperTransport technology

standard

LAB control signal

Each LAB contains dedicated logic for driving control signals to its LEs.

Control signals include two clocks, two clock enable, two

Async Clear, Synchronous Clear, Async Preset/Load,

Synchronized load, plus/minus control signal. This gives

Up to 10 control signals at a time. While synchronizing loads and

Clear signals are often used when implementing counters, they can

Can also be used with other functions.

Each LAB can use two clocks and two clock enable signals. of each laboratory

The clock and clock enable signals are linked together. E.g,

A specific LAB that uses the labclk1 signal will also use labclkena1. if

LAB uses both the rising and falling edges of the clock,

Lab-wide clock signal. Deactivating the clock enable signal will turn off

LAB-wide clock.

Two asynchronous clear signals and one asynchronous signal can be used per LAB

Load/preset signal. when

Asynchronous load data input is pulled high.

Using LAB-wide addnsub control signals, a single LE can implement

1-bit adder and subtractor. This saves LE resources and improves

Performance of logic functions such as DSP correlators and signed

A multiplier that alternates between addition and subtraction, depending on

on the data.

LAB row clock [7..0] and LAB local interconnect to generate LABwide

control signal. Inherent low skew of MultiTrackTM interconnects

In addition to data, clock and control signals are also allowed to be distributed. Figure 2-4

The LAB control signal generation circuit is shown.