AD6688 RF Diversity and 1.2GHz BW Observation Receiver

AD6688BBPZ-3000

AD6688BBPZRL-3000

AD6688-3000EBZ imported original genuine product-Shenzhen Yujixin Electronics Co., Ltd.-Mobile phone/WeChat same number: 13430772257

The AD6688 is a 1.2 GHz bandwidth, mixed-signal, direct radio frequency (RF) sampling receiver. It includes two 14-bit 3.0 GSPS analog-to-digital converters (ADCs) and numerous digital signal processing blocks consisting of four wideband digital downconverters (DDCs). The AD6688 has on-chip buffers and sample-and-hold circuitry to ensure low power consumption, small package size, and excellent ease of use. This product is specifically designed to support communications applications where direct sampling of analog signals with bandwidths up to 5 GHz is possible. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is fully optimized to provide a wide input bandwidth, fast sampling rate, excellent linearity, and low power consumption in a small and compact package.

The dual-channel ADC core utilizes a multi-stage differential pipeline architecture with integrated output error correction logic. Each ADC is equipped with a wide bandwidth input that supports a variety of user-selectable input ranges. An integrated voltage reference simplifies design considerations. The analog input and clock signal are differential inputs. The ADC data outputs are internally connected to the four DDCs through a cross-multiplexer. Each DDC includes up to five cascaded signal processing stages: a 48-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters. The NCO allows selection of preset frequency bands (up to three frequency bands can be selected) on General Purpose Input/Output (GPIO) pins. The operation of the AD6688 can be selected between multiple DDC modes through an SPI programmable configuration file.

In addition to the DDC module, the AD6688 is equipped with several other functions to simplify the automatic gain control (AGC) function in communication receivers. The programmable threshold detector can monitor the power of the incoming signal by using the fast detect control bits in register 0x0245 of the ADC. The quick detect indicator goes high if the input signal level exceeds a programmable threshold. Due to the low latency of this threshold indicator, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect output capability, the AD6688 also has signal monitoring capabilities. The signal monitoring module provides additional information on the signal being digitized by the ADC.

Users can configure subclass 1 JESD204B based high-speed serialized outputs in a variety of one-, two-, four-, and six-wire configurations, depending on the DDC configuration and the acceptable wire speed of the receiving logic device. In addition, multi-device synchronization is supported through the SYSREF± and SYNCINB± input pins.

The AD6688 also offers flexible power reduction options that can significantly reduce power consumption when necessary. All of these functions are programmable through a 3-wire serial interface (SPI).

The AD6688 is available in a lead-free 196-ball BGA package and can operate over an ambient temperature range of ~40°C to +85°C.

Product Highlights

The wide full power bandwidth supports IF sampling of signals up to 9GHz (-3dB point).

Four integrated wideband decimation filters and NCO modules support multiband receivers.

Fast NCO switching via GPIO pins

The flexible SPI interface controls many different product features and functions to meet specific system requirements.

Programmable fast overrange detection and signal monitoring.

On-chip temperature diodes for system thermal management.

12mm x 12mm 196-pin BGA package

application

Diversity Multiband, Multimode Digital Receiver

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A

DOCSIS 3.0 CMTS Upstream Receive Path

HFC Digital Reverse Path Receiver

Advantages and Features

Product Details

JESD204B (subclass 1) encoded serial digital output

Supports line rates up to 16 Gbps per line

1.7 W total per channel at 3 GSPS (default setting)

?2 dBFS amplitude, 2.6 GHz input performance

SFDR = 70dBFS

NSD = ~148.0 dBFS/Hz

?9 dBFS amplitude, 2.6 GHz input performance

SFDR = 75dBFS

NSD = ~151.4 dBFS/Hz

Integrated input buffer

Noise Density = ?152.0 dBFS/Hz

0.975 V, 1.9 V and 2.5 V DC power supply

9 GHz analog input full power bandwidth (?3 dB)

Amplitude Detection Bits for Efficient AGC Implementation

2 integrated wideband digital processors per channel

48-bit NCO

4 cascaded half-band filters

Phase Coherent NCO Switching

Provides up to 4 channels

Serial control

Integer clock with divide by 2 and divide by 4 options

Flexible JESD204B line configuration

On-chip jitter