PH300: Peak Hold Detector. Company advantage inventory.

The Model PH300 is a high performance thin film hybrid peak hold unit designed to track and hold the peak value of an analog input signal with a rise time (10% to 90% of Vmax) as short as 250 ns. The unit also has the lowest holdover voltage sag rate and consumes less than 36 mW in quiescent mode. Laboratory and commercial applications include nuclear physics. Portable Instruments; Nuclear Monitoring; Aerospace; Particle, Gamma, and X-Ray Imaging; Medical and Nuclear Electronics; and Optoelectronic Systems.

Application field

Aerospace

Portable Instruments

nuclear monitoring

Particle, X-ray and Gamma-ray detection

imaging

research experiment

Medical and Nuclear Electronics

Electro-optical system

feature

Operates from -55oC to +125oC

Small size (16-pin hybrid DIP)

Very low power (36 mW static)

high speed

low sag rate

Ramp discharge

quick reset

Built-in linear door

Internal hold capacitor

High reliability screening one year warranty

Inside is the analog input for the PH 300. This input accepts a positive signal. The input signal should not drive more than the positive analog supply, or less than -0.5V Schottky diode input protection. The range is 0 to (V)+-1.5 V).

2V–(-5V to -6V)

3RCEXT is the node that allows the connection of an external hold resistor and hold capacitor. RCEXT is not connected when using internal holdout components.

4HRES is the node for the internal hold resistor.

5 Hz is the node for the internal hold capacitor. This node is usually connected to HRES and DSCHG.

6DSCHG is a node of the current generator used to reset the holding capacitor of the PH 300. The ramp reset current is set by an external current source or external resistor. When the PH 300 is in holdover mode, this node is in a high impedance state. Typically, this node is connected to an HCap node.

7 Isset is a node of the current mirror that sets the discharge current. This node receives positive current. The discharge current at this node is twice the current. An external resistor R should be connected between ISET and ground. In this case, the reset current is set to approximately 2*(V) – +0.6 V/(R + 500 ohms). Amptek recommends a minimum value of 1k for the external resistor. Notice! To ensure proper PH 300 tracking mode operation, the reset current must be set regardless of the reset scheme (ramp or dump) used to discharge the holding capacitor.

8GND

9 Dump (Activity Low) is a TTL compatible signal used to quickly reset the PH 300. This signal can only be used with ramp signals. The dump signal can only be active when the ramp is active. The low state of this signal causes the discharge current to peak at 20 mA, resulting in rapid discharge of the holding capacitor. The duration of the dump signal should be as short as possible, as the high reset current greatly increases the power consumption of the PH 300. A fixed duration of 1 is usually sufficient to completely reset the built-in hold capacitor. The PKDT signal can be used as an indicator of the discharge of the holding capacitor and can provide a function to control the duration of the dump signal.

Ramp 10 (active low) is a TTL compatible input that controls the linear discharge of the PH 300. When this signal is low, the DSCHG node receives current that resets the hold capacitor. Since the reset current is constant, the output of the PH 300 decays linearly.

Gate 11 (high open) is a TTL compatible logic input that controls the PH 300's linear gate. When the gate is active high, the linear gate is opened and the PH 300's error amplifier can sense the input signal. When the gate is not working, the error amplifier input is tied to ground.

12PKDT means TTL output for PH 300 status. When this signal is low, the PH 300 is in hold mode.

13Vd (+5V)

14V+(+5V to +12V)

15 CommScope Node for frequency compensation of the PH 300 when using an external hold capacitor. In this case, a resistor between 20 and 100 ohms can be used to reduce the oscillation of the output signal. This resistor must be connected between COMP and V. +...COMP must be connected to V when using an internal hold capacitor. +.

16 out is the analog output of the PH 300. This output is protected against shorts to ground or any voltage between ground and the positive analog supply. warn! Shorting the output to any negative voltage can destroy the PH 300 circuit. This output can drive capacitive loads up to 50 PF (typ). For higher capacitive loads, use a 50 to 100 ohm series resistor. The range is 0 to (V)+-1.5 V), typical.

charging method

The holding capacitor is charged within the rise time of the input signal. The rise time of the input pulse can be up to 250 ns. When the PH 300 is in charge mode, negative feedback is applied to the amplifier through a high impedance output buffer. Under this condition, the output voltage follows the input signal and the peak detector logic output is inactive. The feedback circuit brakes as soon as the input passes the maximum level and begins to decay. The PH 300 then goes into hold mode.

hold mode

In this mode, the charging diode is reverse biased and the voltage of the holding capacitor remains equal to Vmax. The peak detector logic output is active. The leakage current of the element connected to the hold capacitor discharges it. The rate of this discharge is the PH 300 drop rate.

Discharge method

The holding capacitor can be intentionally discharged by enabling the reset circuit within the PH 300. Two types of resets are possible. They are: (I) Ramp or Linear Reset and (Ii) Dump or Fast Reset.

In Ramp Discharge mode, the hold capacitor is discharged through constant current pull set by an external resistor or external current source. Constant current discharge causes the holding voltage to drop linearly. This mode of operation is used in Wilkinson-type analog-to-digital converters.

In the fast discharge mode, the holding capacitor is discharged for a short period of time by drawing a large current. The frequency and duration of this operating mode determines the upper limit of the device's power consumption.

tracking mode

If the hold capacitor voltage is less than or equal to the voltage at the amplifier's input, negative feedback to the amplifier (and correspondingly the peak detector logic output goes inactive) will become active (and the corresponding peak detector logic) during discharge mode operation output goes inactive). Therefore, if the holding capacitor discharges at a rate higher than the decay rate of the input signal, the output of the PH 300 will follow the input even as the signal decays. This mode of operation of the PH 300 is called Track Mode.

Input Protection - Warning

The input (Pin 1) of the PH 300 is connected directly to the input of the CD 4066 quad bilateral switch. VDD, the positive power supply for this chip, is connected to V+ (+5 to +12 V), PH 300 and VSS of Pin 14 are connected to GND, Pin 8. Normal precautions for using CD 4066 must be followed with PH 300 to avoid damage. ...these precautions include keeping the input voltage within (VSS-0.5V) and (Vdd+0.5V).

In particular, care should be taken that these conditions are not violated at power-up or power-down, or when connectors are mated or unmated with power.

Input protection can be provided by a current limiting resistor (>200 ohms) in series with the input, or by connecting a diode from the input (pin 1) to ground (pin 8) and anode ground.