Features

3.3V logic interface TTL logic level input

Intelligent logic for power -powered/hot insertion state control

[[

123] single -chip integrated circuit reliability

low match Ron

8226; Flexible switching time can be converted from a ringtone mode to a call mode.

Clean, bouncing switch

level three -level protection, including integrated flow limit, voltage clamping and SLIC protection heat shutdown

5V operation, power consumption lt; 10 mw

smart battery monitor

]

16 -needle small SOIC packaging

Application

voip gateway

CO)

Digital Ring Road Carrier (DLC)

pbx system

Digital adding main line (DAML)

# 8226; Hybrid fiber coaxial cable (HFC)

Fiber in the ring (Fitl)

Channel Bank

Note

CPC7592

is a member of the next -generation line card access to the switch series of the Ixys Integrated circuit department. This single -piece six -polar solid switch is encapsulated by 16 -shot SOIC. It provides necessary functions to replace two 2-Form-C electrical relays on traditional simulation and modern integrated voice and data (IVD) line cards (located in the central office, access and PBX devices). Because the device contains a solid switch for cutting -edge and ring lines, ringing/return and test access, it only needs+5V power to operate, and the logical level input is used for control.

CPC7592 is very similar to CPC7582, adding a logical input that is controlled by controlling startup status and TTL compatible.

CPC7592BC logic provides an alternative test status from CPC7592bA/BB, and also provides greater protection of SCR trigger and maintaining current rated values.

Order information

Figure 1: CPC7592 box diagram

function description

Introduction

CPC7592XA and CPC7592XB logic status [123 123 [123 ]

Talk: The disconnect switch SW1 and SW2 are turned off, the bell switch SW3 and SW4 are turned on, and the test switch SW5 and SW6 are opened.

ringtone: disconnect switch SW1 and SW2, turn off the bell switch SW3 and SW4, test switch SW5 and SW6 open.

test: disconnect switch SW1 and SW2, disconnect the bell switch SW3 and SW4, the ring test switch SW5 and SW6 closed.

All off: disconnect switch SW1 and SW2, disconnect the bell switch SW3 and SW4, test switch SW5 and SW6 open.

CPC7592XC logic status

Talk: Disted switch SW1 and SW2 off, the bell switch SW3 and SW4 open, test switch SW5 and SW6 open.

ringtone: disconnect switch SW1 and SW2, turn off the bell switch SW3 and SW4, test switch SW5 and SW6 open.

Test/Monitoring: The disconnect switch SW1 and SW2 are turned off, the bell switch SW3 and SW4 are turned on, and the test switch SW5 and SW6 are turned off.

ringing test: disconnect switch SW1 and SW2, turn off the bell switch SW3 and SW4, and turn off the test switch SW5 and SW6.

All off: disconnect switch SW1 and SW2, disconnect the bell switch SW3 and SW4, test switch SW5 and SW6 open.

CPC7592 uses simple TTL -level logic input control to provide the function of first break, then, and then break, and switch from bell to the call status. The solid switch structure means that the pulse noise will not produce during the switch during the circular frequency or ring check, thereby eliminating the need for the external zero -cross switch circuit. The state control is input through the TTL logic level, so there is no additional driving circuit. Linear cuttings SW1 and SW2 have very low R and excellent matching features. The smallest opening of the SW4 of the bell switch SW4 is 465 V at the minimum opening of the+25 ° C, which has appropriate protection to prevent a breakdown when the transient failure (ie, transmitting the transmitted transmission to the bell generator) occurs. Essence

CPC7592 integrates over -voltage clamp circuits, active current limit and thermal check mechanisms, providing protection for SLIC under failure. Positive and negative thunderbolt poured currents have reduced the overflow circuit, and the dangerous potential passes throughThe diodes of the diodes or optional integrated protection SCR transfer from SLIC. The current limit and the heat shutdown circuit also reduces the power crossing potential.

In order to protect the CPC7592 from being affected by voltage failures, auxiliary protectors need to be used. The secondary protector must limit the voltage at the tip and ring terminal to the level below the maximum breakdown voltage of the switch. In order to minimize the stress on the solid -state contact, it is strongly recommended to use a folding or pry rod -type secondary protector. After the correct selection of the secondary protector, using the CPC7592 line card will meet all related ITU, LSSGR, TIA/EIA, and IEC protection requirements.

CPC7592 is powered by a +5 V power supply. This allows the device to consume very low in any state in any state. The battery voltage used by CPC7592 has dual function. It is used as a reference and current source for internal integrated protection circuits under surge. Second, as a reference. In the case of the battery voltage loss, the CPC7592 will enter the state.

IOU -voltage switching circuit

Introduction

Intelligent logic in CPC7592 now provides switching status control during power supply and power -off conversion. The internal detector is used to evaluate the VDD power supply to determine when the VDD rising voltage switch locks the lock -up circuit, and when to use the decreased VDD to determine the lack of the underwriting switch locking circuit. At any time, if there is a low -VDD condition that is not satisfactory, the locking circuit will use the information that blocks the external input pin and adjust the internal switch command into a full state, thereby covering the user switch control. After the VDD is restored, the switch will be kept in the state until the lock input is pulled down.

The locking of the release of the release of the release of the release of the release threshold is set internally to ensure that all internal logic is properly biased and normal before receiving the external switch command from the input to control the switch state. For the reduction of the VDD event, setting the locking threshold to ensure that the switch is forced to turn off and the external input is suppressed, the logic and switching behavior are normal.

In order to facilitate thermal insertion and power control, there is an integrated weakly pull -up resistor on the VDD power rail on the VDD power rail, which keeps non -driving insertion sales in a logical high level state. This allows the circuit board designer to use CPC7592 with FPGA and other devices that provide high impedance output during power -power and configuration. When the system's lock control driver has a low -minimum absorption capacity of 4mA, the weakly pulling fan output is up to 32.

Precautions for the design of heat plug -in and power -on circuits

Six possible startups may occur during power -on. They are:

1. All inputs defined when power -on and lock 0

2. All inputs defined when power -on and 闩 lock 1 And 闩 lock z definedAll inputs

4. During the power of power and 闩 闩 0, all inputs

5. All inputs are not defined when all inputs and 闩 lock 16. When all inputs are not defined when the power supply and lock z

In all the startups listed above, the CPC7592 will keep all its switches in a full disconnection during power. When meeting the VDD requirements, LCA will complete its startup program in one case in three cases.

For the startup solution 1, when VDD is valid, CPC7592 will transition from the state of the full level to the input definition of the input definition

For the launch solution 2, 3, 5, and 6, CPC7592 will be in the full level The state is powered on and kept in this state until the lock is low. This allows inserting a board that is inserted into the power supply system but not configured with the service.

The launching plan 4 will start when all switches are in the whole level, but the premise is to accept valid VDD, LCA will return to one of the legal states listed in the real value table. After that, it may be cited according to the input quotation Foot leakage current and load are randomly changed. Because under this start -up conditions, the LCAS state after power -on cannot be predicted, this state should not be used.

For the design of the lock pins that do not want to control the multi -port card alone, multiple (or all) lock pins buses can be used to create a single board input and enable control.

Switching logic

Start

CPC7592 Use intelligent logic to monitor VDD power supply. When the VDD is lower than the internal setting threshold, the intelligent logic will put the control logic in the state. After the startup, the internal pull of the insertion office locks the CPC7592 in the whole state until the insertion is pulled down to the low logic. Before asserting the logic of the lock -up office, the switch control input must be adjusted appropriately.

Timber Timing

When from the bell rising state to the call state, use simple TTL logic level input to control the bell switch SW3 and SW4 relative to the release timing of the switch SW1 and SW2 state. ability. These two available technologies are called first -combination, then disconnection and first -after and then combined operation. When SW1 and SW2's disconnection switch contacts are closed (closed) before the bell switch contacts of SW3 and SW4 are closed (closed), which is called first closed and then disconnected operation. When the ringing contacts of the SW3 and SW4 are disconnected (disconnected) before the switch contacts of SW1 and SW2 are closed (closed), the operation occurs first. In CPC7592, by entering the sequence of appropriate logic levels for device applications, it can easily complete the operation of first -pass, then, and then break.

Out operation-All versions

To use the first-to-collaborate operation, please change the logic input directly from the bell state to the call state. When the SW1 and SW2 are closed at the disconnect switch,Apply a call state open the backbell switch SW3. The bell switch SW4 is kept closed until the ringing current is over zero. When it is in a preconceived state, the bell potential that exceeds the CPC7592 protection circuit threshold will be transferred from SLIC.

Play before and after-the interruption of all versions of the ringing to the call conversion logic sequence

Operation-CPC7592XA/B

CPC7592XA/B first break and then combined operation can be achieved using two different technologies.

The first method uses the operation of IN and IN logic input, as shown in the middle:

1. At the end of the bell, the full customs state (1,1) is applied. When the bell switch (SW4) keeps open, release the bell return switch (SW3) to wait for the next zero current event.

2. Maintain at least half of the ringing period in the whole level to ensure that the occurrence of parts has occurred, and the bell switch SW4 has been opened.

3. Enter input for the need for the next state. For call status, input to (0,0).

When the bell switch is turned on before the switch SW1 and SW2 are turned off, it will be broken first and then.

Pre-break --- Make the ringing call transition logic sequence CPC7592XA/B

Pre-manufacturing operation-All versions

CPC7592XA /B's ""Two Interruption Before Closing"" method is also the only available method for CPC7592XC. As shown in Hedu, the two -way T interface disables all CPC7592 switches when pulling the logic. Although logically disabled, an activated (closed) bell switch (SW4) will be closed until the next over -current event.

As shown in the table, this operation is similar to the operations shown in the middle. In addition to the method of selecting the full customs state, and the operation when the input and input are re -configured to the call state.

1. Pull TSD to the lower limit of logic and end the belling state. This will turn on the bell switch (SW3) and prevent any other switch off.

2. Keep the TSD low in half of the ringing cycle, so that there is enough time to occur with zero current events, and the circuit enters the first break and then the state.

3. In the low time of TSD, set Inring and Intest input to call status (0,0).

4. Remove the TSD and allow the interior to start the interrupted switch.

When using TSD as input, the proposed two states are ""0"