Features

Standardized symmetrical output features

mid -speed operation: –Tphl, TPLH 30ns, 10V (typical)

#8226; Test static current at 20 V under 20 V 18 V, the maximum input current is 1 μA

The packaging temperature range, 18 V and 25 ° C are 100 na

Meet the tentative requirements of jedec

standard 13B, B series CMOS device description of the standard specification

123] pulse plastic surgery

oscillator

High input impedance amplifier

CD4069UB

The device consists of six CMOS inverter circuits. These devices are suitable for all general inverter applications, which do not require medium -power TTL drivers and circuit logic level conversion capabilities, such as CD4009 and CD4049 HEX inverters and buffers.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

CD4069UB function figure

Typical features

Parameter measurement information

Detailed explanation Overview ] CD4069UB equipment has six inverter circuits. The proposed working range is 3 V to 18 V.CD4069UB series with 14 needle seal dual -column direct -inserted ceramic packaging (F3A suffix), 14 -pin dual -column direct -inserted plastic packaging (E suffix), 14 -needle small epithelial packaging (M M M M , MT, M96, and NSR suffix) and 14 needle thinner contraction (PW and PWR suffix).

Function box diagram

Feature description

CD4069UB has standardized symmetrical output characteristics, from 3V to 18 V, static current is 20 V v Test. There is a medium working speed -tphl, TPLH 30 ns (typical values) at 10 V under 10 V. The operating temperature is -55 ° C to 125 ° C. CB4069B conforms to JEDEC No. 13B TemporaryAll requirements of the standard B -series CMOS Device Description Standards .

Device function mode

Table 1 shows the function mode of CD4069UB.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification. TI does not guarantee its accuracy Or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

Within the entire packaging temperature range, the CD4069UB device has a low input current of 1 μA at 18 V, and has a low input current of 100 mA under 18 V and 25 ° C under 18 V and 25 ° C. Essence This device has a wide operating voltage range from 3 V to 18 V for high -voltage applications.

Typical application

Design requirements

CD4069UB device is the highest logical inverter in the industry. The working voltage of working voltage under the proposed conditions is to be the proposed conditions. 18 volts. The lower driver capacity makes it suitable for light loads like LED, and greatly reduce the chance of over -rushing and owed.

Detailed design program

The recommended input conditions in FIG. Recommended VIH and VIL under run conditions). The input is not resistant to overvoltage and must be lower than the VCC level, because VCC has input clamping diode.

Recommended output conditions for CD4069UB applications include specific load current. The load current must be limited to make it not exceeding the total power (continuous current through VCC or GND) device. These limits are located in absolute maximum rated values. The output must not be pulled to VCC.

Application curve

Power suggestion

The power supply can be the minimum and maximum rated power supply voltage, located at the recommended operating conditions Essence

Each VCC pin must have a good bypass electrical container to prevent power interference. For single power equipment, TI is recommended to use 0.1-μF capacitors. If there are multiple VCC pins, TIs are recommended to use 0.01-μF or 0.022-μF capacitors per power. It is acceptable to connect multiple bypass containers to suppress different frequencies. 0.1-μF and 1-μF capacitors are usually used together. The installation of bypass containers must be as close as possible to the power to get the best results.

Layout

Layout Guide

When using multiple logic devices, the input cannot float.

In many cases, the function or part of the digital logic device function or these functions is unused (for example, when using only two inputs of the triple input and the door, or only 3 of the 4 buffers of the doorTo.This input pin cannot be kept discontinuous, because the unarmed voltage of the external connection will cause an unfarished operating state.In all circumstances in the next paragraph, this rule must be obeyed.

All unused inputs of digital logic devices must be connected to high or low bias to prevent them from floating.For more information about floating input effects, please refer to the meaning of the application, the meaning of slow or floating CMOS input (SCBA004).According to the function of the device, the logic level must be applied to any unused input.Usually, they are connected to GND or VCC (prevailing for convenience).

layout example