THCV217: V-by-One? HS high-speed video data transmitter and receiver. Company advantage inventory.

THCV218

THCV226

THCV216

THCV234

THCV220

THCV219

THCV236

THCV235

THCV231

General Instructions

THCV217 and THCV218 are designed to support

Video data transfer between host and display.

1 high-speed lane can carry up to 32-bit data and 3 high-speed lanes

Sync signal bit on pixel clock

Frequency from 20MHz to 85MHz.

The chipset features two high-speed data channels,

Video data up to 1080p/10b/60Hz can be transmitted. of

The maximum serial data rate is 3.4Gbps/lane.

feature

?Color depth optional: 24(8×3)/32(10×3)bit

?Single-in/single-out, single-in/dual-out and

Dual input/dual output of THCV217 optional

?Single-in/single-out, dual-in/single-out and

Dual input/dual output of THCV218 optional

?AC coupling of high-speed lines

feature

?Color depth optional: 24(8×3)/32(10×3)bit

?Single-in/single-out, single-in/dual-out and

Dual input/dual output of THCV217 optional

?Single-in/single-out, dual-in/single-out and

Dual input/dual output of THCV218 optional

?AC coupling of high-speed lines

Functional Overview

With V-by-One™HS proprietary coding scheme and CDR (Clock and Data Recovery) architecture,

THCV217 and THCV218 support 8/10-bit RGB, 2-bit user-defined data (CONT) transmission,

Sync signals HSYNC, VSYNC and DE via single/dual differential pair cables with minimal external signals

components.

The transmitter THCV217 inputs CMOS data (including video data, CONT, HSYNC, VSYNC and DE) and

Depending on the polarity of DE, the video data and sync signals are serialized separately. DE is a signal

Indicates whether video or sync data is active. When DE is high, it serializes the video data input to

Differential data flow. When DE is low, it sends serialized sync data.

Figure 1 is a conceptual diagram of the basic operation of the chipset.

The receiver THCV218 automatically extracts the clock from the incoming data stream and converts it to serial

Identify video data with DE high or synchronize data with DE low to identify

Serial data is being sent by the transmitter. And the recovered data is output in the form of CMOS data.

The THCV218 can operate over a wide range of serial bit rates from 600Mbps to 3.4Gbps/lane.

Figure 2 shows a timing diagram of the basic operation of the chipset.

It does not require any external frequency reference, such as a crystal oscillator.

data enabled

There are some requirements for the DE signal, as described in Figure 1, Figure 2 and Table 18.

If DE = low, the control data has the same period, and the data bits "CTL" may be specially assigned, except for the first and

The last pixel is transmitted. Otherwise, video data is transmitted during DE = high.

The control data from the receiver during DE = high is the previous data of the DE transition. See Figure 2.

The high and low lengths of DE are at least 2 clock cycles, as shown in Table 18.

Data enable must be toggled periodically, eg high->low->high.

CTL bit transfer

There are specific allocated data bits "CTL" that can be transmitted when DE=high and DE=low

Except for the first and last pixel on DE=Low.

This feature is enabled by setting the THCV218 Reserved7 pin high