THCV216: V-by-One? HS high-speed video data transmitter and receiver. Company advantage inventory.

General Instructions

THCV215 and THCV216 are designed to support

Video data transfer between host and host

show.

The chipset can transmit 39bit video data and 3bit

Synchronize data over only one differential cable

LVDS clock frequency from 20MHz to 100MHz.

The chipset features two high-speed data channels,

Can transmit video data up to 1080p/10b/60Hz,

1080p/12b/60Hz. The maximum serial data rate is

3.75Gbps/lane

feature

?Selectable color depth: 6/8/10/12 bit

?Single/Dual link optional

?AC coupling

?LVDS input internal termination

?CORE 1.8V, LVDS 3.3V

? Package: 64-pin TSSOP

?Wide frequency range

?CDR does not require external frequency reference

? Support Spread Spectrum Clocking: Maximum

30kHz/?0.5% (center spread)

?Compliant with V-by-One?HS Standard Version1.4

Function Description

Functional Overview

With V-by-One™ HS proprietary coding scheme and CDR (Clock and Data Recovery) architecture, THCV215

And THCV216 can transmit 18/24/30/36-bit video data per pixel (Rn/Gn/Bn/CONTn), Hsync

(HSYNCn), Vsync (VSYNCn) Data and Data Enable (DE), via single/dual differential pair cable

external components.

Transmitter THCV215 inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video

Data and Hsync, Vsync data are separated depending on the polarity of DE. DE is a signal indicating whether

Video or H-Sync, V-Sync data is active. When DE is high, it serializes the video data input into a single differential

data flow. When DE is low, it transmits serialized Hsync, Vsync data.

The receiver THCV216 automatically extracts the clock from the incoming data stream and converts it to serial

The data is converted into video data whose DE is high or Hsync, and Vsync data whose DE is low, identify which type

Serial data is being sent by the transmitter. And output the recovered data in the form of LVDS data.

The THCV216 can operate seamlessly over a wide range of serial bit rates from 600Mbps to 3.75Gbps/lane,

Detects the frequency of the incoming data stream and recovers clock and data separately.

It does not require any external frequency reference, such as a crystal oscillator.

Data Enablement Requirements (DE)

As described in Figure 2, Figure 3 and Table 15, there are some requirements for DE.

The dual LVDS inputs of the THCV215 should be synchronized according to DE transitions. See Figure 2.

If DE = Low, the same cycle of Hsync and Vsync data is transmitted. Otherwise, the video data will be transmitted

(DE = high). The SYNC data from the receiver during DE = high is the previous data of the DE transition. See Figure 3.

The high and low lengths of DE are at least 2 clock cycles, as described in Table 15.

Data enable must be toggled periodically, eg high->low->high.

THCV217

THCV218

THCV226

THCV216

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THCV220

THCV219

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THCV235

THCV231