APA600-BG456I: Field Programmable Gate Array. Company advantage inventory.

Features and Benefits

High capacity

Business and Industry

?75,000 to 1 million system gates

? 27 K to 198 Kbit two-port SRAM

? 66 to 712 user I/O

military

?300,000 to 1 million system gates

? 72 K to 198 Kbit two-port SRAM

? 158 to 712 user I/O

Reprogrammable Flash Technology

?0.22 μm 4 LM Flash-based CMOS process

? Live Power On (LAPU) level 0 support

?Single chip solution

?No device configuration required

? Retain programming during power-down/power-up cycles

?Military/aviation equipment can operate at full military temperature

scope

performance

?3.3 V, 32-bit PCI, up to 50 MHz (military 33 MHz

temperature)

?Two integrated PLLs

? External system performance up to 150 MHz

Safe programming

?The industry's most effective security key (FlashLock?)

low power

?Low impedance flash switch

?Segmental Hierarchical Routing Structure

?Small, efficient, configurable (combined or sequential)

logical unit

High-Performance Routing Hierarchy

?Super fast local and long-distance network

?High-speed ultra-long line network

? High performance, low skew, splittable global network

? 100% routable and utilization

input Output

?Each input has Schmitt trigger option

?2.5 V / 3.3 V support, voltage can be selected individually

and slew rate

?Bidirectional global I/O

? Compliant with PCI Specification Revision 2.2

? Boundary scan test IEEE standard. Compliant with 1149.1 (JTAG)

? Pin-compatible packages for the entire ProASICPLUS family

Unique clock conditioning circuit

? PLL with flexible phase, multiply/divide and delay

ability

? Internal and/or external dynamic PLL configuration

?Two LVPECL differential pairs for clock or data input

Standard FPGA and ASIC Design Flow

?Flexibility to choose industry-standard front-end tools

?Efficient design with front-end timing and gates

optimization

ISP support

?In-system programming (ISP) via JTAG port

SRAM and FIFO

?SmartGen netlist generation ensures optimal use

Embedded memory block

? 24 SRAM and FIFO configurations with synchronization and synchronization

Asynchronous operation up to 150 MHz (typ)