APA075-PQG208I: FPGA - Field Programmable Gate Array. Company advantage inventory.

Features and Benefits

High capacity

Business and Industry

?75,000 to 1 million system gates

? 27 K to 198 Kbit two-port SRAM

? 66 to 712 user I/O

military

?300,000 to 1 million system gates

? 72 K to 198 Kbit two-port SRAM

? 158 to 712 user I/O

Reprogrammable Flash Technology

?0.22 μm 4 LM Flash-based CMOS process

? Live Power On (LAPU) level 0 support

?Single chip solution

?No device configuration required

? Retain programming during power-down/power-up cycles

?Military/aviation equipment can operate at full military temperature

scope

performance

?3.3 V, 32-bit PCI, up to 50 MHz (military 33 MHz

temperature)

?Two integrated PLLs

? External system performance up to 150 MHz

Safe programming

?The industry's most effective security key (FlashLock?)

low power

?Low impedance flash switch

?Segmental Hierarchical Routing Structure

?Small, efficient, configurable (combined or sequential)

logical unit

High-Performance Routing Hierarchy

?Super fast local and long-distance network

?High-speed ultra-long line network

? High performance, low skew, splittable global network

? 100% routable and utilization

input Output

?Each input has Schmitt trigger option

?2.5 V / 3.3 V support, voltage can be selected individually

and slew rate

?Bidirectional global I/O

? Compliant with PCI Specification Revision 2.2

? Boundary scan test IEEE standard. Compliant with 1149.1 (JTAG)

? Pin-compatible packages for the entire ProASICPLUS family

Unique clock conditioning circuit

? PLL with flexible phase, multiply/divide and delay

ability

? Internal and/or external dynamic PLL configuration

?Two LVPECL differential pairs for clock or data input

Standard FPGA and ASIC Design Flow

?Flexibility to choose industry-standard front-end tools

?Efficient design with front-end timing and gates

optimization

ISP support

?In-system programming (ISP) via JTAG port

SRAM and FIFO

?SmartGen netlist generation ensures optimal use

Embedded memory block

? 24 SRAM and FIFO configurations with synchronization and synchronization

Asynchronous operation up to 150 MHz (typ)

The ProASICPLUS family of devices, the second generation of Actel

Flash FPGA family offering enhanced functionality

Better performance than Actel's ProASIC series. it combines

Advantages of ASIC vs. Programmable Advantages

Devices through non-volatile flash technology. this

Enables engineers to create high-density systems using

Existing ASIC or FPGA design flow and tools. also,

ProASICPLUS family offers unique clock adjustment

The circuit is based on two onboard Phase Locked Loops (PLLs).

This family offers up to one million system doors,

Supports two-port SRAMs up to 198 kbit and beyond

Up to 712 user I/Os, all offering 50 MHz PCI performance.

The designer's advantages are not limited to

performance. Unlike SRAM-based FPGAs, its four levels

Routing hierarchy simplifies routing while using flash

Technology enables all functions to take effect at power up.

Support device without external boot PROM

programming. Airborne Safety Mechanisms

block access to program information,

Reprogramming can be performed in the system to support

Future design iterations and field upgrades. equipment

Architecture eases ASIC migration complexity

with a higher number of users. This makes ProASICPLUS cost-effective

solutions for web applications,

Communications, Computing and Avionics Markets.

The ProASICPLUS family achieves its non-volatility and

Through advanced flash-based reprogrammability

0.22 μm LVCMOS process with four layers of metal.

Standard CMOS design techniques are used for

Implement logic and control functions, including

PLL and LVPECL inputs. This results in predictable

Performance is compatible with gate arrays.

The ProASICPLUS architecture provides granularity

Comparable to gate array. Device core includes

A sea of tiles? Each tile can be configured as a trigger,

Latches or three-input/one-output logic functions

Program the corresponding Flash switch.

Combination of fine-grained, flexible routing

Resource, rich flash switch can be 100%

Utilization and 95%+ routable for high congestion

design. Tiles and larger functions connect to each other

Through a four-level routing hierarchy.

Embedded two-port SRAM block with built-in FIFO/RAM

Control logic can have a user-defined depth and width.

Users can also choose to program to synchronize or synchronize

Asynchronous operation and parity generation or

examine.

Unique clock conditioning circuitry in each device

Includes two clock conditioning modules. each block

Provides PLL core, delay line, phase shift (0° and

180°), clock multiplier/divider and

circuitry required to provide bidirectional access

The phase-locked loop PLL block contains four programmable

Divider allows input clock signal

Divide by a variety of factors from 1 to 64.

The clock conditioning circuit also delays or advances

Input reference clock up to 8 ns (with

0.25 ns). PLL can be configured internally or

Externally during operation without redesign

Reprogram the part. In addition to the PLL,

There are two LVPECL differential input pairs to accommodate

High-speed clock and data inputs.

In order to support the needs of customers more comprehensively,

Low-Cost Board-Level Test, Actel's ProASICPLUS

The device is fully compliant with IEEE Standard 1149.1

Used to test access ports and boundary scan test architectures.

More about Flash FPGAs

implementation, see "Boundary Scan

(JTAG)" section, pages 2-8.

ProASICPLUS devices offer a variety of high performance

Plastic Packaging. those packages and

The performance characteristics discussed above are

There are more details in the following sections.