Features

A single 3.3V power supply

High -performance clock generator, including the crystal oscillator circuit of the integrated frequency synthesizer

low output jitter, as low as 380 FS (RMS integrated between 10 kHz –20 MHz)

low phase noise at high frequency; at 708 MHz, at 10 KHz at 10 KHz Small than -109 DBC/Hz, less than -146 DBC/Hz

support from 27.35 MHz to 38.33 MHz from 10 MHz. ; Output frequency range from 10.9 MHz to 766.7 MHz, from 875.2 MHz to 1175 MHz

Low-voltage differential signal (LVDS) output, 100- Different film outer terminal, 10.9-mHz to to 400 MHz frequency range

Differential low-voltage positive ejaculation logic (LVPECL) output, 10.9-MHz to 1.175-GHz frequency range

Voltic control oscillator (VCO) supports wide output frequency range

fully integrated programmable loop filter

LVDS mode is 240 mega Tile, LvpeCL mode is 300 MW

chip enable control pin

Simple serial interface allows programming after manufacturing

Non -loss -loss memory (EEPROM) on the integrated film, can store settings without applying high pressure to the device

mold or QFN24 packaging

ESD protection More than 2 KV HBM

Industrial temperature range -40 ° C to 85 ° C

low cost, high -frequency crystal oscillator oscillator

Description

CDCE421

is a clock generator of high -performance, low phase noise. It has two completely integrated, low noise, LC-based voltage control oscillator (VCO), and the operating frequency range is 1.750-2.350-GHz. It has an integrated crystal oscillator that works with external AT crystals to generate a stable frequency benchmark for PLL -based frequency synthesizers.

Output frequency (fOUT) is proportional to the frequency of input crystals (FXTAL). Pre -splitter, feedback frequency division, output frequency division, and VCO selection are relative to (FXTAL) settings (FOUT). For the required frequency, check Table 1 and find the corresponding settings in the same line. Use Formula 1 to calculate the accurate crystal oscillator frequency required to output.

Output allocation (1) 1, 2, 4, 8, 16, or 32

Feedback distribution (2) 12, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 20 or 32

(1), the output allocation and the feedback allocation should come from the same line in Table 1.

(2), the feedback division is set automatically according to the pre -splitter in Table 1.

The high -level box diagram of CDCE421 is shown in Figure 1.

CDCE421 supports a differential LVDS clock output or a differential LVPECL output.

All device settings can be programmed through the simple serial interface of Texas instruments.

The device works in the 3.3V power supply environment, which is characterized by working between -40 ° C to 85 ° C.

CDCE421 has molds or QFN-24 packaging.

In CDCE421, the feedback binsea is automatically set according to the pre -splitter. The product of the pre -splitter and the feedback frequency division is 60 or 64, as shown in Table 1 to maintain the stability of the control circuit.

Equipment settings and configuration

(1), the feedback frequency division is set automatically according to the pre -splitter.

(2), the frequency range is not continuous

Device setting example

The following example illustrates the process of cutting crystals required to generate the required output frequency.

Assuming the output frequency of 622.08MHz is required, Table 1 shows the expected output frequency between 583.5 and 680MHz.

(1), the feedback frequency divider is set automatically according to the pre -splitter.

Therefore, this means that the device must be configured:

vco vco 1

Output allocation 1

Prepatic frequency settings 3 [[[[[[[[[

123]

In order to determine the correct crystal frequency required to obtain 622.08MHz under these settings, the numerical is replaced by the square 1.

AT's frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz). As shown in Table 1)Essence

Serial interface and control

CDCE421 uses a unique Texas instrument proprietary interface protocol, which can be configured and programmed through the single input pins of the device. The architecture allows only to write from this input pin to the device. The contents of the reading register can be achieved by sending the read command and monitoring output PIN (LVDS or LVPECL) on the input Pin. When the output pin cannot be used to read the content, the software that controls the interface must explain the content and programming time of writing EEPROM. Monitor the output verification programming mode, and recycling whether the EEPROM is maintained correctly configured.

CDCE421 can be configured and programmed through SDATA input pins. To this end, the Fangbo's program must be written into the device, as described in the following section. In the EEPROM programming phase, the device needs a stable VCC of 3.3 V ± 100 MV to write the EEPROM unit safely. After each WordX is written, the written data is locked and effective, and provides forward -looking before the actual data is stored in EEPROM.

The following table summarizes all effective programming commands.

(1), each rising edge will cause one bit to be locked.

(2), between the throne, some longer delays may occur, but this has no effect on the data.

(3), the length of WordX is expected to be 10 bits. After 10th place, the corresponding words are locked, and the effect can be observed as a forward -looking function.

Enter the programming mode FIG. 3 shows the timing behavior to write data to sdata. The display sequence is 00 1100. If the high cycle is shorter than T1, it is explained as 0. If the high cycle is the same as T3, it is explained as 1. This behavior is achieved by converting the input signal SDATA to the signal SDATA_Dlayed. As shown in Figure 3, SDATA_Dlayed can be used for locking (or selection) SDATA. The timing specifications of T1 -T7, TR and TF are shown in Figure 3.

EEPROM programming

Load all registers in RAM by writing Word0 to Word5. After returning to State 2, enter State 3 (Programming (Programming EEPROM, not lock) or status 4 (locking programming on EEPROM), and the content of Word0 -Word5 is stored in EEPROM. When programming for EEPROM, wait for 10 milliseconds in state 3 or 4, and then turn to Status 2 (idle state).

Note: When the function tests and verification is performed through the serial bus writing device, only accessRAM.

Example: 6 -character programming cycle and EEPROM programming

The following sequence shows how to enter the programming mode and how to write different words. Word 0 ... The address of Word 5 is displayed in thick body. After the word address, the effective load of the corresponding words is recorded. In this example, the next step is to enter EEPROM programming with EEPROM lock from Status 2 → Status 3. In EEPROM programming state, you need to wait at least 10 milliseconds to be safe. The last command is to jump from Status 3 to State 1 (normal operation). Re -power and confirm whether the device runs according to the program.

Enter the regulator back reading mode and related time sequential diagrams

Similar to entering the programming mode sequence, enter the register read mode to write SDATA. After the command is issued, the SDATA input is re -configured to the clock input. By applying a clock, the EEPROM content is read into the displacement register. Now, by applying clocks on SDATA, EEPROM content can be output and observed at the clock at OUTP/OUTN. There are 59 places for time. As the 61st clock rises, the output/output pin is configured to work normally.

The following table summarizes the output ratio. It should be noted that digest 0 is first punched in.

Packaging (mold)

CDCE421 has molds or QFN 24 sticks. The position and number of the mold version pad are shown in Figure 5.

pads instructions

Table 2 shows the pin description of the CDCE421 mold.

Packaging (qfn24)

CDCE421 also uses QFN 24 packaging. The area of u200bu200bthe QFN package is displayed. The position and number of the pads and numbers are shown in Figure 6.

Pipe instructions

Table 3 shows the pins description of CDCE421 QFN-24 package.

Output (LVPECL or LVDS)

CDCE421 equipment has two sets of output drives, LVPECL and LVDS, the output is line or together. You can only choose one output at a time; the other enters a high impedance state (Hi-Z).

If the device is configured to LVPECL, the output buffer is transferred to Hi-Z, and the terminal resistance determines the state of the output under the device disable mode (CE L) (LVPECLP LVPECLN Hi-Z). If the device configurationFor the LVDS mode, if the device is banned (CE L), the output will be transferred to Hi-Z.

The jitter characteristics in the input clock mode

Use the LVCMOS input signal driver to package the CDCE421 device in the QFN-24 package to perform the jittering characteristics test.

The reference of CDCE421 by 35.42MHz and a cleaner LVCMOS input reference, Figure 8 shows from 708MHz from 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz to to 100Hz 40MHz output SSB phase noise diagram. Pay attention to the dependence of the output jitter to the input reference jitter. The test settings are shown in Figure 13.

For CDCE421 being cleaned by 33.33MHz input, FIG picture. The test settings are shown in Figure 12.

Appendix A: Test configuration Test settings to describe the CDCE421 device in the exchange and DC terminal. The figure below illustrates all four settings for the clock signal driven by the tested device.

Appendix B: Packing The packaging and wiring of CDCE421 is responsible for the oscillator supplier.

CDCE421 is designed in a commonly used 6 -pin oscillator packaging. Among them Design CE together.