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2022-09-16 16:00:09
CDC706 is a programmable 3-PLL clock combined device/multiplicator/cousin
Features
Based on 2: 6 PLL, a high -performance clock formor/multiplication instrument/division
User programmable PLL frequency
easily perform online programming through the SMBUS data interface
wide PLL frequency division ratio allowed 0-ppm output clock error
accept single-end CMOS clock input or LVA differential inputcan receive the crystal frequency of 8 MHz to 54 MHz
support up to 200 MHz LVCMOS or differential input frequency
Two programmable control input [s0/s1], the control signal for user definition
six LVCMOS output, the output frequency is as high as 300 MHz
[ 123] LVCMOS output programming can be complementary signal
through the programmable output switch matrix [6x6] freely select the output frequency, including 7 rear frequency frequency divisions of each output [123 ]
Integrated PLL ring filter componentLow cycle jitter (Typical 60 PS)
Reduce the system EMI
used to reduce the programmable output conversion rate control of the system EMI (SRC)
3.3V device power supply
# 8226; Industrial temperature range -40 ° C to 85 ° C
Easy PLL design and programming development and programming tool (Ti Pro clock #8482;)
# 8226; 20 -needle tssop packaging
Factory programmable customized default settings. For more details, please contact the TI sales department.
Application
wireless base station
network card
data communication/telecommunications
Terminal allocation
Explanation
CDC706
The input frequency can be entered by LVCMOS, differential input clockOr a single crystal export. You can select appropriate input waveforms through the SMBUS data interface controller. Deep M/N dividing frequency ratio allows zero PPM clock to generate zero PPM clock from any reference input frequency (e.g., 27 MM).
CDC706 includes three PLLs, one of which supports SSC (spreading clock). The design frequency of PLL1, PLL2, and PLL3 is as high as 300 MHz, and optimized the zero PPM application with a wide -point factors.
PLL2 also supports the center spreading and downlink expansion clock (SSC). This is a common technology to reduce electromagnetic interference. In addition, the rotation rate controlled (SRC) output edges minimize EMI noise.
According to the frequency frequency and frequency division settings, the internal circuit filter element will be automatically adjusted to realize the high stability and optimal jitter transmission characteristics of the lock ring.
The device provides customized applications. It uses the factory default configuration for pre -preparation (see Figure 13), and it can reassemble it to different applications through the serial SMBUS interface.
Two free programming inputs, S0 and S1, can be used to control the most stringent logical control settings of each application (output is disabled to low, output 3, power off, PLL bypass, etc.).
CDC706 has three power pilots, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply of the device. Its operating voltage is 3.3 volts. VCCOUT1 and VCCOUT2 are the output power pins. VCCOUT1 is powered out of Y0 and Y1, and Vcout2 is powered out to output Y2, Y3, Y4, and Y5. The two output power supply can be 2.3 volt to 3.6 volts. When the output voltage is lower than 3.3 volts, the output current driver is limited.
CDC706 is characterized by working at temperatures of -40 ° C to 85 ° C.
Figure Figure
output switch matrix
Application information
SMBUS data interface 
[
123] In order to improve the spirit of the clock combination deviceActivity and functions provide a dual -signal serial interface. It follows the SMBUS specification version 2.0, which is based on the I2C operation principle. 
Data protocol
The serial protocol of the clock driver accept the byte writing, byte reading, block writing, and block reading operation of the controller.
For blocking/reading operations, the bytes must be accessed in order from the lowest byte to the highest byte (the highest effective position in the front), and can stop after transmitting any complete bytes. For byte writing and byte reading operations, the system controller can access the bytes of separate addressing.
Once a byte is sent out, it is written to the internal register and immediately take effect immediately at the rising edge of the ACK bit. This is suitable for the bytes of each transmission, which has nothing to do with whether the byte writing or block writing sequence.
The offset of the indexing byte is encoded in the command code, as described in Table 1.
Figure 9 and Figure 10 outlined block writing and block reading protocols, and Figure 7 and 8 outline the corresponding byte writing and byte reading protocol.
From the receiver address (7 digits)
byte writing editorial sequence
Byte Reading editorial Sequence 
Writing into the editing sequence (1) 
The sequence of the reading editor
SMBUS hardware interface 
The default device settings
CDC706 pre -programming is the default configuration of the factory, as shown below. This will make the device in the working mode without programming it first. The default settings appear after power -on or power -off/power -off, until the user re -programmed it to configure different applications. Programming the new register set by serial SMBUS interface.
Different default settings can be programmed according to customer requirements. For more information, please contact Texas instruments to sell or marketing representatives. 
function description
Clock input (clock input 0 Input 1)
Crystal oscillator input (default settings)
Two independent single -ended LVCMOS inputs 
The input signal source position of byte 11 can be selected by byte 11.
The input frequency range of the crystal oscillator input
The input frequency range of the crystal mode is 8MHz ~ 54MHz. CDC706 uses a Pierce oscillator circuit, which contains feedback resistors used to discharge large vessels. However, users must add external capacitors CX0, CX1) to match the input load capacitors that match the crystal (see Figure 14). You can calculate the required value:
Among them, CL is a crystal load capacitor specified for the crystal unit. CICB is the input capacitor of the device, including board capacitors (PCB's messy capacitors) Essence
For example, for the 27 MHz basic crystals with 9 PF and CICB to 4 PF,
It is important to use the from the device to the crystal unit Short PCB trajectory to maintain the smallest bias capacitance of the oscillator circuit.
In order to ensure the stability of the oscillation, a certain driving power must be applied. CDC706 has an input oscillator with adaptive gain control, and users do not need manual programming gain. The driving level is the power consumed by the oscillation crystal unit, which is usually represented by the power consumed by the resonant (equivalent series resistor (ESR)). Figure 15 gives the relationship between driving level and crystal frequency and ESR.
For example, if the 27 MHz crystal of 50 #8486; 2 x CL is 18 PF, the driving power is 21 μW. Keep the driving level at a minimum value to avoid excessive drive crystals. In the oscillator specification, the maximum power consumption is specified for each type of crystal, that is, the above example is 100 μW.
Single -end LVCMOS clock input
When choosing the LVCMOS clock mode, CLK IU IN0 and CLK_IN1 can be driven to 200 Mikh as the regular clock input pin. Two clock input circuits are equal to designYes, you can use each other independently (see Figure 16). Select 10 digits by internal clocks [4] to select one of the two input clocks. Clk_in0 is the default selection. You can also choose to choose an external control pin S0/CLK_SEL program as a clock choice, byte 10, bit [1: 0]. 
Input
CDC706 also supports differential signals. In this mode, CLK_IN0 and CLK_IN1 pins are used as a differential signal input, which can drive to 200 MI.
The minimum amplitude of the differential input voltage is 100 MV within the input voltage range of 200 MV to VCC – 0.6. If the LVDS or LVPECL signal is applied, it is recommended to use AC coupling and bias structure to adjust different physical layers (see Figure 17). The capacitor removes the DC component of the signal (common mode voltage), while the AC component (voltage amplitude) is passed. The resistance of the resistance upper pull and/or drop -down network indicates that the bias structure of the co -mode voltage is set on the side of the receiver of the AC coupling electric container. DC coupling is also possible.
PLL configuration and settings
CDC706 includes three functions of the same function and performance. In addition to PLL2, it also supports the generation of Loaning Cop (SSC). FIG. 18 shows the frame chart of the loop.
All three locking loops are designed for the simplest configuration. The user only needs to define the input and output frequency or frequency division (M, N, P) settings, respectively. All other parameters, such as the charging pump current, filter element, phase margin, or loop bandwidth are controlled and set by the device themselves. This guarantees the optimized jitter attenuation and circular stability.
PLL supports normal speed mode (80MHz ≤FVCO ≤ 200MHz) and high -speed mode (180MHz ≤ FVCO ≤ 300MHz), which can be selected by PLLXFVCO (Bit of byte 6 [7: 5]). The respective speed options ensure stable operation and minimum jitter.
The frequency division M and the frequency divider N worked as a FVCO frequency division internally, up to 250 MHz. This allows the frequency to output clock error to zero PPM output clock.
If FVCO GT; 250 MHz is recommended to use only an integer factor of N/m.
In order to get the mostGreeting performance, please make the frequency divider m as small as possible. In addition, the concept of score removal requires PLL removal, m≤n (or n/m≥1). 
PLL bypass and
VCO bypass
[123
] In the PLL bypass mode, PLL is completely bypass, so the input clock is directly switched to the output switch A (Swapxx of byte 9 to 12). In the VCO bypass mode, by setting the PLLXMUX to 1 (Bit of byte 3 [7: 5]), only the corresponding PLL VCO is bypass. However, the removal Mer M is still available and extended the output removal of an additional 9 digits. In this way, a total frequency frequency frequency range of m x p u003d 511 x 127 u003d 64897 is obtained. In the VCO bypass mode, the corresponding PLL block is broken and the current consumes the current.
(1), the P removing instrument includes the output switch matrix in the calculation.
(2), FVCO≤250 MHz score operation.
(3), FVCO GT; 250 MHz integer operation.
Reduce the expansion and clock interference
In addition to the basic lock -in -loop function, PLL2 also supports the expansion clock (SSC). Therefore, PLL2 has two outputs, SSC output and non -SSC output. Two outputs can be used parallel. The average phase of the center expansion SSC modulation signal is equal to the phase of the non -regulating input frequency. SSC is selected by the output switch A (Swapxx of byte 9 to 12). 
In high -speed applications, SSC is an effective way to reduce electromagnetic interference (EMI) noise. It reduces the radio frequency energy peak of the clock signal by modulating frequency and extend the energy of the signal to a wider frequency range. Because the energy of the clock signal remains unchanged, the frequency of widening the pan -sounding will inevitably reduce the amplitude of the pan -sound. Figure 19 shows the effect of SSC on the DSP 54 MHz clock signal.
The peak range of the modulation clock is 11.3dB lower than the unopened carrier frequency to reduce the electromagnetic energy of the expansion and radiation.
In SSC mode, users can choose SSC modulation volume and SSC modulation frequency. The modulation volume is based on the frequency deviation of the carrier (minimum/maximum frequency), and the modulation frequency determines the speed of frequency change. In the SSC mode, the maximum VCO frequency limit is 167 MHz.
SSC modulation volume
CDC706 supports center spread and downward modulation. In the central extension, the clock moves symmetrically around the load frequency, which can be ± 0.1%, ± 0.25%and ± 0.4%. At the time of expansion, the clock frequency is always lower than the carrier frequency, which can be 1%, 1.5%, 2%, and 3%. If the system cannot tolerate the operating frequency of the nominal frequency (overnight clock problem), the preferred downward expansion.
Example: 
(1), 54 MMH -carriers of 0.5%expansion is equivalent to 59.865 Mixhe when the center expansion ± 0.25%.
SSC modulation frequency
The modulation frequency (scanning rate) can be selected between 30 kHz and 60 kHz. It is also based on the VCO frequency shown in the SSC modulation frequency. As shown in Figure 20, the damping increases as the modulation frequency increases. It may be limited by the downstream loop tracking deviation. CDC706 uses triangular modulation configuration files, which is one of the common configuration files of SSC.
further reduces electromagnetic interference
The best damping is a combination of modulation, modulation frequency and the harmonic considers. Please note that due to the large frequency deviation, the frequency of high -end harmonic waves will cause stronger EMI.
As shown in Figure 21 and 22, the slower output conversion rate and/or smaller output signal amplitude help to a greater extent to reduce EMI transmission. Both measures have reduced the clock harmonic radio frequency energy. CDC706 allows the conversion rate control between 0.6NS and 3.3ns (byte 19-24, bit [5: 4]). The output amplitude is set by two independent output power supply voltage pins VCCOUT1 and VCCOUT2, ranging from 2.3 to 3.6 volts. Even the output power supply voltage as low as 1.8 volt can work, but the maximum frequency must be considered.
Multi -functional control input S0 and S1
CDC706 has two users' defined input pins, can Use as an external control pin or address pin. When programming is to control the pin, they can be used as clocks to select pins, enable/disable pins or equipment. If both tube feet are used as address positions, up to four devices can be connected to the same SMBUS. Each function is set in byte 10; bit [3: 0]. Table 4 shows the possible settings of different output conditions, clock selection and device address.
(2), if S0 is 0, select CLK_IN0; if S0 is 1, select CLK_IN1.
As shown in Table 4, different output conditions have a specific order: the power -off mode covers 3 states, 3 states cover low state, and low state covers activity status.
The flexible structure of the output switch matrix
The flexible structure of the output switch matrix allows users to switch any internal clock signal source to any of the six outputs through the free selected rear segmentation device. 
Switching B is added to the output switch matrix to ensure that the output frequency of a P splitter is aligned by 100%. In addition, the construction method of the P-removing weapon is that each method of division can automatically correct the duty ratio. Dynamic changes may cause the output to fail.
In addition, the output can be switched to active, low or 3 and/or 180 degrees. The output conversion rate and output voltage are also available by users.
LVCMOS output configuration
The output stage of CDC706 supports all common output settings, such as enlightenment, disable, low state and signal reversal (180 degrees shift). It also has a conversion rate control (0.6ns to 3.3ns) and the voltage of variable output power supply (2.3V to 3.6V).
All output settings can be programmed by SMBUS:
enable or disable to low position → byte 19 to 24, bit [3]
Transfer → byte 19 to 24, bit [6]
Conversion rate control → byte 19 to 24, bit [5: 4]
→ VCCOUT1 (pin 14) and VCCOUT2 (pin 18) 
Performance data: output deviation, jitter, cross -coupling, noise suppression (confusing suppression) and phase noise
Output deviation
Deeping is an important parameter of the clock distribution circuit. It is defined as the time difference between the output of the same input clock driver. Table 5 shows the high-low and low-high conversion output deviation of the CDC706 in the entire power supply voltage, working temperature, and output voltage swing range (TSK (O)).
Judging performance
Judging is a main parameter of the clock driving circuit based on the lock -locking ring. As the speed increases and the time budget decreases, this becomes very important. The design of the CDC706 and the internal circuit design is minimal jitter. The peak cycle jitter is only 60ps (typical). Table 6 gives the peak and average square root deviation of periodic jitter, cyclical jitter, and phase jitter during the characterization process.
(1), all typical values u200bu200band maximum values u200bu200bare VCC u003d 3.3 V, temperature u003d 25 ° C, vccout u003d 3.3 V; More than 10,000 cycles.
Figure 26, Figure 27, and Figure 28 show the relationship between period to cycle jitter, cycle jitter and phase jitter from the period to the period of 10,000 samples. The jitter changes as the sampling window becomes smaller or wider. During the week, the jitter and cyclical jitter display the measurement value, and the phase jitter is a cumulative cyclical jitter.
TJIT (CC) is a change in the clock signal cycle time between the neighboring cycle of the neighboring cycle pair. During the week, the jitter will never be greater than the cycle jitter. It is also called adjacent cycle jitter. 
The cycle signal is the cycle time deviation of the clock signal relative to the ideal cycle (1/fo) on a random cycle sample. As far as the ring is concerned, the cycle jitter is the worst case of the cycle deviation of the loop output in the ideal situation. This is also called short -term jitter.
Phase jitter (TJIT (phase)) is the long -term change of the clock signal. It is a cumulative deviation of the control edge relative to the average value of T (θ) in a random circular sample. In the literature, phase jitter, time interval error (TIE), or drift is used to describe long -term changes in frequency. In ITU-T: G.810, the drift is defined as a phase change with a rate of less than 10Hz, and the jitter is defined as a phase change greater than 10Hz. The measurement interval must be long enough to obtain meaningful results. Drift can be caused by temperature drift, aging, and power supply voltage drift.
The jitter depends on the VCO frequency (FVCO) of the locked loop. Compared with lower FVCO, higher FVCOs produce better jitter performance. The frequency of the pressure -controlled oscillator can be defined by locking M and N splitters in the loop.
Since the CDC706 supports a relatively wide frequency range, the device provides VCO frequency selection bits, that is, bits of byte 6 [7: 5]. This bit defines the frequency range of the jitter optimization of each PLL. Users can be between normal speed mode (80 MHz to 200 MHz) and high -speed mode (180 MHz to 300 MHz)Select. Figure 29 shows the jitter performance of FVCO within two frequencies.
Ti-PRO clock software automatically calculates the PLL parameter to optimize the jitter performance.
Cross -coupling, bruises and noise suppression
The cross -coupling in the integrated circuit is achieved by the interaction between several parts of the chip, such as between output levels, metals, metals and metals Between lines, between cables, between substrates, etc. This coupling can be coupling of capacitors, inductors, and resistance (ohms) caused by the output switch, leakage current, ground bouncing, and power transient. 
Good isolation is a major criterion using the BICMOS process because it can minimize the coupling effect. Even though all three locking loops are activated and all outputs are opened, the noise suppression is significantly higher than 50 decibels. Figures 30 and Figure 31 show the examples of noise coupling, bandate inhibitory and power noise suppression of CDC706. The measurement conditions of the mold are shown in Figure 30 and Figure 31.
Phase noise characteristics
In a high -speed communication system, the phase noise characteristics of the phase frequency synthesizer of the lock phase frequency have attracted much attention. The phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter specification in the time domain.
Phase noise is the result of a wide slope and false peak value caused by random and discrete noise. Disclosure components may be caused by the clock frequency, power cord interference and mixer products known in the signal source. The width caused by random noise rising is caused by phase noise. It may be the result of thermal noise, scattered noise, and/or flash noise in the active and passive devices.
An important factor of the synthesizer of the lock phase frequency is the circuit bandwidth (-3DB cut -off frequency). Essence The LBW of CDC706 is about 100kHz to 250kHz, depending on the selected PLL parameter.
For CDC706, the two phase noise characteristics are interesting: phase noise of the transistor input stage and the phase noise of the internal lock ring (VCO). Figure 32 shows their respective phase noise characteristics.
Some applications use frequency switching, that is, change the frequency in TV applications (switch between channels) or in a computer in a computer Change the PCI-X frequency. The time spent on realizing the new frequency is the main interest. The lock time is jumping from one specified frequency to another within a given frequency to anotherThe time required for the specified frequency (see Figure 33). It should be very low because the long lock time will affect the data rate of the system.
PLL locking time depends on the device configuration, and can be changed through the VCO frequency, that is, by changing the value of the M/N divisor. Table 7 gives a typical lock time of the CDC706, and FIG. 33 shows the snapshot of the frequency switch.
(1) The result of the crystal lock time (200 μs) and PLL lock time (100 μs).
Power sorting
CDC706 includes three power supply feet VCC, VCCOUT1 and VCCOUT2. Because the three power nodes are separated from each other, there is no power sorting requirement. Therefore, power can be powered on three nodes in any order.
In addition, the component has a power -on circuit. When VCC exceeds 2.1 V (typical values), the circuit will turn on the device; when VCC is less than 1.7 V (typical values), the circuit will turn off the device. In the power -off mode, all output and clock inputs are turned off.
Equipment behavior when the power supply voltage decreases 
In the case of a decrease in power supply voltage, the power -on circuit ensures that there is always a defined setting in the register. Figure 34 shows the possible voltage drop at different amplitude.
CDC706 -pass power circuit has a built -in lag. If the voltage is kept above VPUC_OFF (usually 1.7 V), the contents of the register remain unchanged. If the voltage drops below the VPUC U OFF, the internal register is re -loaded by the ROM after the VPUC U ON is crossed again. VPUC_ON is usually 2.1V. Table 8 shows the contents of the ROM and register after the above voltage is reduce