Features

Suitable for car applications

AEC-Q100 Qualification

Drive

Drive 6 independent N -channel power MOSFETs, up to 250 NC gate charging

Source/exchange), convenient for output slope adjustment

conforming to all FET/40 v overmusted sensors

separate control input of each power MOSFET [123 123 [123 ]

PWM frequency is as high as 30 kHz

support 100%duty occupy ratio operation

operating voltage: 4.75 to 30 v

Since the voltage converter is integrated to generate the voltage of the grid drive, the power supply voltage runs normally

logic function dropped to 3V

#8226; Short -circuit protection, with VDS monitoring and adjustable detection level

two integrated high -precision current detection amplifiers, two gains can be programmed second -level, and there is a low load current in operation. Higher resolution

Overwriting and under pressure protection

Have a programmable dead area protection function

Real -time phase comparator

over -temperature warning and shutdown

complex fault detection and treatment through the SPI interface

battery; battery; Reverse Protection to -4 V (with series protection resistance)

Sleep mode function

Packaging: 64 -pin HTQFP POWERPAD #8482;

Application

Car Safety Key Motor Control Application

- Electric help steering system (EPS, EHPS) [123 123 ]

- Electronic braking/braking assistance

- Transmission

- Oil pump

Industrial security key motor control application

Explanation

Bridge driver is dedicated to automotive three -phase brush -free DC motor controls including safety -related applications. It is a normal level N -channel MOSFET transistorProvide six special drivers. The driver's function is designed to process 250 NC's gate charges, and the driver source/exchange current can be programmed to facilitate the output slope adjustment. The device also integrates complex diagnosis, protection and monitoring functions through the SPI interface. A voltage converter with an integrated field effect transistor provides over -drive voltage, allowing fully controlling the power level, even if the battery voltage is low to 4.75V.

Figure Figure

Detailed description

DRV3201-Q1

Design Used to use pulse width to control three -phase brush -free DC motors in automotive applications. The three high -side and three low -side door drives can be switched separately, and the transmission delay is very low. Enter logic to prevent the high and low -pressure drives of the same channel at the same time. You can access the configuration and status register through the SPI communication interface.

Supply concept

The battery voltage working range of DRV3201-Q1 is between 4.75 V and 30 V. DRV3201Q1 uses 3.3 V or 5 V MCU, which can be implemented by connecting the MCU's IO voltage to the VDD_IO pin of DRV3201-Q1, and connecting the ADC reference voltage of the MCU to the ADREF pin of DRV3201-Q1. All digital output is associated with VDDIO, all analog output is related to Adref (clamp). Except for EN pin, all digital inputs are related to internal power VCC3. The working voltage of the grid drive of the external power field effect of the transistor is 4.75 volt. When the power supply voltage is lower than 4.75V, the grille of the external FET is actively lowered. When the power supply voltage is lower than 3V, the gate is semi -actively pulled down. The minimum startup battery voltage of the door drive and internal logic is 4.75 V.

Internal logic from the voltage range of the full -function battery (ie, between 4.7 V and 30 V), including the SPI interface, can work even when the battery voltage drops to 3V. When the battery voltage drops below 3V, the DRV3201-Q1 triggers a complete internal reset to remove all internal status bits and registers. In addition, when DRV3201-Q1 logic reset, SPI communication with MCU is disabled.

VCC5 is an internal power supply of a current influenza amplifier and other internal analog circuits. The VCC5 pins need to use a typical 4.7NF capacitor for external decoupling. VCC5 has internal current limits to avoid any internal damage due to short circuit on the external land on the VCC5 pin.

VCC3 is the internal power supply of internal logic. The VCC3 pin needs to be decoupled with a typical 4.7NF capacitor. Since VCC3 is powered by the VCC5 regulator, its output is limited by VCC5 current, so short circuit outside the VCC3 pin outsideIn the case, it can avoid any internal damage. If the VCC5 pin or VCC3 pin is short -circuited on the ground and the internal logic is reset, the MCU can detect this because SPI communication is disabled. In this case, it is strongly recommended that the MCU takes necessary measures to turn off the EN pin and close the DRV3201-Q1 to avoid the overload time of VCC5 and/or VCC3.

The booster converter

The voltage converter is configured to provide additional voltage to the power supply voltage. The Boost converter requires an external inductance, capacitor, Schottky diode, and a ground resistor for current. The high -voltage and low -voltage side grid drives are powered by the booster converter. This allows DRV3201-Q1 to realize the full range of door-driven voltage of all external power FET, even when the battery voltage drops to 4.75 V. There is a separate B -EN pin to enable/disable. When the device is in a dormant mode, the boost converter cannot be enabled.

Sleep mode/activity mode

EN (enable) pin to make the device enter the sleep mode. After the decrease of the EN pin, after the typical 6 μS depression time, the grille of the external power FET is actively lowered by the gate drive. Later (minimum 20μs, maximum 35 μs) internal power supply VCC5, VCC3, boost converter, and current detection amplifier were turned off, and the grille of the external power FET was pulled down by a semi -active drop resistor (see the semi -active drop resistor). Internal logic is placed in a reset state, and all internal registers are cleared. There is no use diagnostic information in the sleep mode.

The rising along the EN pins enables the device to be in the activity mode after the TBD power power. In the activation mode, the power VCC5 and VCC3 exist, and can be enabled or disabled by the B_EN pin. Since all internal registers are cleared in the dormant mode, after waking up from the dormant mode to the activity mode each time, the MCU must program DRV3201-Q1 programming as the required settings.

Digital input/output pins

Except EN pins, all digital input pins (the bids in the terminal menu are HVI_D) have a threshold voltage related to the internal VCC3 power supply. Therefore, regardless of whether the VDDIO level exceeds restrictions, the state of these input pins is effective. These digital input pins have a fault security ESD structure, only the reverse diode path to the ground, and there is no reverse diode path to any power supply voltage. Depending on the function, these input pins have an internal passage of pulling down or pulling up. All digital output pins (labeled LVO_D) have a pushing level between VDDIO and the ground. Therefore, the logic high level is related to VDDIO.

Reset

DRV3201-Q1 can be reset by switching RSTN to a low level. When RSTN is low, allThe status position and register settings are cleared, the Boost converter and the current detection amplifier are closed, and the grid drive output is effectively lowering, the maximum setting is the leakage current, so as to turn off the external power FET. When RSTN is compulsory to low, the internal power supply VCC3 and VCC5 are still valid. The input high and low thresholds of RSTN are related to VCC3, so it has nothing to do with VDDIO. Therefore, regardless of whether the VDDIO level exceeds the limit, the status of the RSTN pin is effective.

The door drive

DRV3201-Q1 has three high-voltage and low-voltage side grid drives. Each high -side and low grille drive contains a programmable source and sinking current to charge the grille for external power field effects crystals.

Digital logic prevents a power -level high and low -pressure door drives at the same time. If you detect the activation command from the MCU while the MCU is detected, the bid failure in the state register is faulty.

The slope control of the gate driver

The design of the DRV3201-Q1 supports adaptive slope control. The grille of the external power FET is charged and discharged through the programmable exchange current and source current. Table 1 shows the leakage current and sources of the sources of the grille driver.

In order to reduce the risk of twisted slopes due to changing the slope settings, the Singjia setting of the rising edge is only after the next decrease of the affected gate drive. vice versa. This is not applicable to the use of the activity mode directly. As long as the low -voltage side or high -voltage side door drive is switched to the activation mode after waking up, the slope setting of the programming setting is immediately activated.

In order to achieve the high scalability of the output FET and the switch speed, there is a general -purpose reduction of the current mode setting, which is 25%of the compatibility/discharge current set. In addition, by setting the bit 7 in the configuration register 1 (CFG1) to 1, the driver can be set to the switch mode. In this settings, the driver is not limited by the current, and can limit the switch speed with a resistor in the grille line in the external grid. In this mode, it is strongly recommended to set the slope register (CURR0–3) to 0x3F to obtain the maximum current settings, and only the current limit of the external resistor.

Direct mode (6 x input operation)

Direct mode is the default operation mode every time you wake up from sleep mode to activity mode. In the direct mode, all the doorsteps can be controlled separately through digital input pins IHSX/ILSX.

PWM mode (3 x input operation)

Or, set the bit 6 in the configuration register 1 (CFG1) to 1, you can operate the grid drive in the PWM mode. The PWM mode only controls all six door drives with three PWM signals. PWMThe effective control in the mode is IHSX input. When all security functions are maintained, the low -side control is exported by the corresponding IHSX signal. In the PWM mode, ILSX input can be used as a SPI readable universal input.

The door drive is closed

When the DRVOFF pin is high -electricity, the output of the gate drive will be effectively lowering and the external power FET is turned off by setting up the Sink current programming settings. At the same time, IHSX/ILSX input can be read back through SPI. Enable VDS comparators and logo errors (if VDS is too high), which can be used to ensure the functions of these blocks. When DRVOFF is forcibly reduced, the Boost converter, current detection amplifier, and internal VCC3 and VCC5 power supply are still active. DRVOFF's input high and low threshold are related to VCC3, which has nothing to do with VDDIO. Therefore, regardless of whether the VDDIO level is exceeded, the status of the DRVOFF pin is effective.

Actively pull down

When the external power supply FET needs to be closed and the DRV3201-Q1 is in the activation mode (through normal control signals, DRVOFF signals, RSTN signals or any error processing), the door drive provides low ohm with low ohm has some ownership Pull the source. When the grid voltage of the transistor of the power field effect is lower than 2V, the programmatic current exchange behavior is transformed to RDSON behavior to increase the drop -down intensity.

Semi -source pull -off resistor

Each high, low -voltage side drive has a typical 500 kΩ resistor. The effects crystal tube is closed without power supply. In addition, the semi -proactive drop -down circuit reduces the grid impedance when the typical voltage is 2V to about 7kΩ. This semi -active drop -down circuit is closed during normal operation to avoid higher DC current consumption of the gate drive.

The closing path of the gate drive

Table 2 summarizes the possible state of EN, RSTN, and DRVOFF pins and the impact on the door drive.

(1), for 3V LT; vs LT; 4.75V, vs under pressure detection actively lower the grille of the external FET. For vs lt; 3V, these doors are half -prolapse.

Security

DRV3201-Q1 has extensive security characteristics and helps the application award high security level.

Monitoring error

The following sections describe the error of monitoring. These errors are described in configurable security mode.

Direct source voltage monitoring

DRV3201-Q1 provides the leakage voltage monitoring function for each external power MOSFET. When the input pin IHSX/ILSX becomes high, open the external power MAfter OSFET, its leakage source voltage was monitored. If this voltage is kept higher than the VDS threshold in the filter time (TVDS), the error will be improved and the state of the power MOSFET will be set.

The internal VDS threshold monitored by VDS monitoring can be set through the external analog input level on the SCTH pin, and the coefficients of the register 0 (CFG0) bits 5: 3 can be configured at 0 and 1 to SPI. Eight steps between them are scaled.

The VDS comparator configuration of each door drive is shown in Figure 5. As shown in Figure 5, the VSH pin is used as a detection input voltage for high -voltage side VDS comparators. On the outside, the VSH pin should be connected to the star -shaped point of the power -level positive power supply.

In order to verify the correct operation of the VDS comparator during the normal operation period, the proportional factor can be reduced through the SPI, or the SCTH voltage can be reduced from the outside. This will set a lower VDS threshold (mainly depending on the random comparator's offset lt; ± 100 mv), which will cause the comparator to switch under the relative low current of the external power (no current during normal operation). As shown in Figure 6. During this verification process, you can deal with the error treatment of VDS errors in accordance with the configuration security mode (configured register 1 (CFG1), bit 3: 4), so that VDS errors can only be quoted in the SPI state register 0 (STAT0) and ERR lead Mark on your feet. The SCTH pin is a high impedance input into the MOS gate, which has internal ESD grounding protection. No power supply has a reverse upward path (fault safety ESD structure).

Direct detection and programmable dead zone time

DRV3201-Q1 provides a mechanism to prevent two external MOSFETs of each power level connected at the same time at the same time connected at the same time Pass, and connect VS directly to GND. If the digital input is trying to force the device to switch a power -level high -voltage and low -voltage side grille drive, the error in the state register increases and switch the bridge according to Figure 7.

The dead area can be divided into eight steps between the 200 NS and 3000 ns of the registers 0, bit 2: 0. The dead time of programming is effective for all three power levels. The internal 10 MM oscilloscope is used as the time benchmark for creating a dead area step.

When running in a direct mode, the dead zone time can be banned in the configured security mode (see configurable security mode). The PWM mode does not support prohibited programming dead areas.

Ratial pressure error error

If the output voltage of the boost converter is lower than the IOUS of TBCSD (5 μs – 6μs) Set up the boost in the SPI Statue Register 1 (STAT1)IOU. According to the configuration security mode (see the configuration security mode), all door drives are pulled down and the ERR pins are pulled down.

VS owed pressure stop

If VS voltage is lower than the low -voltage threshold level VVS, TV's UV (4.5 V -4.75 V), SHD (5μs – 6μs), then in the SPI state state The VS underwriting logo is set in the register 1 (STAT1). This will happen regardless of the security mode of configuration (see the configuration security mode). The working voltage of the SPI interface is 3 V. Internal reset occurred when below 3 V.

VS overvoltage error

If VS voltage exceeds the overvoltage threshold level VVS, OV (30 V -30.5 V) The sign is set in SPI status register 1 (STAT1). According to the configuration security mode (see the configuration security mode), all door drives are pulled down and the ERR pins are pulled down.

VS comparator check

VS under pressure and over -pressure comparator can be checked by clock loss (LOC) test/vs comparator position in the use of configuration register 0 (CFG0). As long as this bit is set, the comparator will switch and label under pressure and overpressure at the same time. Error treatment is in a state of activity, so the bridge is closed and the error pin is pulled down. To reset the logo, you need to reset the LOC TEST/VS comparative position, and then need to read the logo through the SPI. After that, the ERR pins rose again. This self -test is combined with the loss of clocks (see the loss of the clock).

Super temperature warning and shutdown

The thermal overload detection and protection of the device is based on five temperature sensors and two threshold TMSD1 (thermal warning) and TMSD2 (hot global reset):

[

123]

The device runs normally:

The door drive and the boost converter can work.

Thermal warning -ultra -temperature warning signs set to 1:

heat warning, stored in the overheating warning position of status register 0 (STAT0). The place was reset after reading the register in the MCU.

Global reset-device is in a closed state:

generate internal reset.

Breathing converter stops.

but the temperature monitor module monitor the temperature, and the reset was released until the temperature dropped below TMSD0.

heat lags can avoid any oscillation between stop and restart.

ultra -temperatureThe stop is filtered by TSHDOWN (unnecessary stopped caused by no noise).

SPI error

If the DRV3201-Q1 receives an invalid writing or read access, the SPI OK bits in Statue Register 1 (STAT1) are set to 0. The bit is set to 1 after reading the register of the MCU.

EEPROM CRC verification

After each awakening to the activation mode, DRV3201-Q1 performs an EEPROM CRC check. If the CRC8 verification is calculated and does not match the CRC8 verification and non -matching of the CRC8 stored in EEPROM, the EEPROM data CRC failure logo is set in status register 1 (STAT1).

Configuration data CRC check

DRV3201-Q1 provides a security feature, which permanently ensure the integrity of the configuration through the CRC8 verification and mechanism. The MCU can set the CRC8 verification and calculation of all configuration registers by setting the bit 0 in the CRC control register (CRCCTL) to 1 in DRV3201-Q1. Before the CRC calculation is completed, the position is kept. The CRC engine may not have any writing access when running, otherwise the CRC8 check and damage will be damaged. The CRC8 verification and value calculated by DRV3201-Q1 are stored in the CRC calculation verification and register (CRCCALC).

The MCU itself can also calculate the expected CRC8 verification and value based on the vector given below, and store the expected value in the CRC expectation verification and register (CRCEXP). This should be completed before the CRC8 verification and calculation of the MCU startup DRV3201-Q1. After the CRC calculation is performed in the DRV3201-Q1, if the expected CRC that is stored in the CRCEXP register does not match the CRC calculated in the CRCCALC register, the configuration data CRC failure logo is set in the status register 1 (STAT1).

Then, the MCU can read back all the configuration registers to search the bit error and perform correction operations.

The CRC8 computing mechanism is a general mechanism with the following preset:

The initial value is: 11111111

CRC data vector is shown in Table 3.

Clock loss

If the internal clock is stuck, the clock loss monitor will pull the ERR pin. During the test of this block, the error rate was also very low. The self -inspection is combined with the VS comparator's self -test (see VS comparator self -inspection).

Configure security mode

DRV3201-Q1 canWorking in two different security modes, controlled by the external pin CSM, as described in Table 4. This pin can be read back through the SPI register RB0.

(1), the stress that exceeds the absolute maximum rated value may cause permanent damage to the equipment. These are just stress rated values. Under these conditions or under any other conditions, the functional operation of the device does not mean functional operations under the proposed operation conditions. Long -term exposure may affect the reliability of the device under absolute maximum rated conditions.

(2), unless otherwise stipulated, all voltage is related to the network ground terminal.

Table 5 defines the protection measures taken under certain errors. When the device is in a complete security mode, all internal protection functions will be activated. If the corresponding error is detected, all the protection measures listed below will be taken. When the device is in configurable security mode (CSM), the error conditions, protection movements, and ERR pin indications available for CSM can be configured to be configured to the corresponding position in CFG1. Regardless of the CSM settings, if there are corresponding errors, the diagnostic signs are always set.

Error instructions on the ERR pin

ERR pin is an indicator that detects the error situation. It can be interrupted as an external MCU, and then the MCU reads all state registers to determine which error is detected. After entering the activation mode, as long as the error is not detected, the pin is kept high. When the error is detected, the error pin becomes lower. Make an error report according to Table 6.

Once the corresponding illegal conditions disappear, after the corresponding error sign in the read state register, the ERR pins rose again. If the MCU reads the corresponding error logo in the state register, and the corresponding error conditions still exist, the ERR pin shows a short positive pulse (the pulse width is usually 100ns).

This behavior helps the difference between clock error loss and vs arrears or over -pressure error signs during the self -inspection process of these security characteristics. After the 6th place (CFG0) in the configuration register 0, the ERR pin decreases. After the MCU reads the status register 1 (STAT1) bit 1: 0, the VS under pressure/overvoltage logo in 1: 0, if the clock self -test is lost normally, the ERR pin should be kept at a low level. If the ERR pin shows positive pulses (pulse width is usually 100 nan seconds), it means that the clock self -test loss fails.

Additional security features

IHSX/ILSX Input Return/Edge Room

In order to verify the signal path to DRV3201-Q1, the device allows itRead the logic levels of all IHSX and ILSX inputs. These values u200bu200bdirectly reflect the state of PIN and do not register. It is necessary to ensure that the status of IHSX and ILSX pins will not change the level by reading through the SPI.

Even if the PWM mode was selected, the IHSX/ILSX input recovery can still work. In this case, ILSX Readback can be used to read any logical level signals.

The edge counter allows the ILSX/IHSX signal chain to conduct more stable and less timely verification of time, and may be more convenient to use during normal operation. This counter can be used to calculate the number of edges on one or more IHSX/ILSX input. The MCU selects the input to be observed and enables the counter by writing the SPI register RB1. When the starting bit is removed, the counter stops the counting edge. You can read the counter value obtained from the SPI register RB2, and reset it by setting the clearance bit in the SPI register RB1.

When the counter reaches the maximum value of 255, it stops counting and maintains this state.

Even if the PWM mode was selected, the IHSX/ILSX edge counter is still in working state. In this case, it can be used to count the edge of the input end of any connection.

Gallery voltage monitoring

DRV3201-Q1 provides door source voltage monitoring function for external MOSFET. For each external MOSFET, VGS is monitored by a comparator, 1V is used as a lower threshold, and 9V is used as a higher threshold.

For each external MOSFET, a status logo is set in SPI state register 2 (STAT2), bit 0: 5. When each VG rises above 9V, each state bit is set to 1, and when the respective VG drops below 1V, they are set to 0. This function is used for the launching diagnosis to open/close the external MOSFET and check their respective positions.

Ultima ratio support

In some cases, all FET may need to be opened at the same time, which is supported by the device. However, in order to minimize the risk of unexpected triggers, two requirements need to be met:

1.mcu needs to perform three different continuous SPI transmission sequences.

2. When the last SPI command is sent, all IHSX and ILSX inputs need to be at a high level.

This function is available only in direct mode.

current measurement

Dual -channel current measurement is measured by voltage on two external stream resistors. It contains a displacement buffer, two first and two secondary.

Show buffer

DRV3201-Q1 provides a unit gain amplifier, which is usually used to support the displacement voltage with lower output impedance. This allows each current detection path to process the negative coefficient voltage of the external stream resistor. The displacement voltage is applied to the RI pin from the outside, and the actual shift voltage is cushioned on the RO pin.

The RI input pin is a high impedance input to the internal ESD protection ground that enters the MOS gate. No power supply has a reverse upward path (fault safety ESD structure).

Two first -level amplifiers

The first -level operation amplifier work with the external resistance network in order to adjust the current measurement value according to the application requirements.

In the recommended application, a shift voltage based on external reference (such as an external voltage regulator) can be added to move the transmission curve. Each channel of the first amplifier has its own output to the input of MCU ADC.

The first level input is highly compatible, so the device can be used to measure the voltage drop of low -side MOSFETs that require low -required applications. The maximum output voltage of O1 and O2 pins is fixed on the Adref voltage.

The input pin INX and IPX pins are high impedance input to the MOS gate, and the internal ESD protects ground. No power supply has a reverse upward path (fault safety ESD structure).

Two secondary amplifiers

The secondary amplifier with a separate programming gain can achieve higher resolution measurement at low current. They can directly connect to the input end of the MCU ADC.

The gain of the second -level amplifier can be programmed using the CFG2 register in step 2, 4, 6, and 8 through SPI.

The maximum output voltage of O3 and O4 pins is ADREF voltage.

ADREF voltage pliers

The maximum output voltage of the pin O1 – O4 is fixed to the voltage of the ADREF by the active clamp. Adref voltage is the reference power supply voltage of the ADC in MCU, so the output O1 -O4 has the maximum signal range related to the ADC input range in the MCU. The maximum current that consumes ADREF pins is 100 μA.

current detection application circuit

The standard configuration of the current influenza amplifier is shown in Figure 10.

O1/2 output voltage is:

O3/4 output voltage is:

, where G is the first one The second -level SPI adjustment gain.

Phase comparator

This device contains three real -time phase comparators, which can be used for non -transmitting direction and diagnosis. Each comparator is usually switched at 75%and 25%of the power supply voltage, and there is a separate digital output to mCU. As long as EN is high, the phase comparator is always activated.

Phase comparator Application Figure

Phase comparator configuration is shown in Figure 12.

The phase comparator allows:

real -time observation of the phase switch on the node SHSX

measure input input Time between IHSX/ILSX and phase comparator output PHXC

verify the time drift of previous measurement and/or other driving phases

As shown in Figure 12, VSH and PGND The pin is used as a detection input to create a high and low -side threshold level for the phase comparator. Connect the VSH pin outside to the star -shaped point of the power level positive power supply. PGND pins are connected to the power -level power ground star shape. The total resistance of the internal storm is usually 248kΩ.

Breathing converter

Boost converter is based on the emergency mode fixed frequency controller. During the connection time, the internal low -side boost field effect transistor will be connected until the current limit level is detected. The time is calculated based on the independent 2.5 MHz time benchmark through the induction power supply voltage VS and output vo