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2022-09-16 16:00:09
CS5166 5 -bit synchronous CPU controller with good power and current limit
Features
■ V2TM control topology
■ Double N channel design
■ 125ns controller transient response
■ Run more than 1MHz [123 ]
■ 5 -bit DAC
■ Good output with internal delay
■ Adjustable HICCUP mode over current protection
■ Completely complete The Pentium II system only needs 21 components
■ 5V and 12V operations
■ Self -adaptable voltage positioning
■ Remote sensing capacity
■ Native flow capacity [ 123]■ VCC monitor
■ Overwriting protection (OVP)
■ Available soft start
■ 200NS pulse width adjustment hidden hidden
[123] ■ 65ns field effect Crystal tube non -overlap
■ 40ns gate lift time (3.3NF load)
Instructions
CS5166
is a synchronous dual NFET Anti -pressure regulator controller. It aims to stimulate the core logic of the latest high -performance CPU. It uses a V2TM control method to achieve the fastest transient response and the best overall adjustment. It contains many additional functions to ensure the normal operation and protection of the CPU and power system. CS5166 provides the highest integration solution in the industry, minimizing the number of external components, the total scale and cost of the solution. CS5166 will work within the voltage range of 4.15 to 14V, and provide 16 -led wide -body surface installation and packaging.Application diagram
300MHz Pentium II is 5V to 2.8V
Block Figure
Operation theory
V2TM control method
V2TM control method uses the slope signal generated by the ESR of the output capacitor. This slope is proportional to the AC current through the main electromoter, and is discharged by the value of the DC output voltage. Because the slope signal is generated by the output voltage itself, this control scheme is inherently compensated to the changes in the line or load conditions. This control scheme is different from traditional technology, such as voltage mode, it produces an artificial slope, a current mode, Generate a slope inductance current.
V2TM control method is shown in Figure 1. The output voltage is used to generate error signals and slope signals. Because the slope signal is only the output voltage, it will be affected by any changes in the output, regardless of what the source of this change is. The slope signal also contains the DC part of the output voltage, which allows the control circuit to drive the main switch to 0%or 100%of the duty cycle as required.
The changes in the line voltage will change the current slope in the inductor, which affects the slope signal, which makes the V2TM control scheme compensate the duty cycle. Because the changes in the inductor current will change the slope signal, the V2TM control scheme has the same advantage in the transient response of the line.
The change of load current will affect the output voltage, thereby changing the slope signal. The loading step is immediately changed to the status of the comparator output, and the comparator output control the main switch. The load transient response is determined by the conversion speed of the comparator in response time and the main switch. Like the traditional control method, the response time of the output load level jump has nothing to do with the cross frequency of the error signal ring.
Because the transient response is processed by the slope signal ring, the error signal ring circuit may have a lower cross frequency. The main purpose of this slow feedback circuit is to provide DC accuracy. The noise resistance is significantly increased, because the bandwidth of the error amplifier can be rolled at low frequencies. The enhanced resistance improves the remote sensing of the output voltage because noise related to the long feedback trajectory can effectively filter.
The BODE diagram in FIG. 2 shows the gain and phase margin of the CS5166 monocular feedback circuit, and shows the overall stability of the regulator based on CS5166.
Because there are two independent voltage circuits, the line and load adjustment have been greatly improved. The voltage mode controller relies on changes in error signals to compensate the deviation of the line or load voltage. The change of the error signal causes the output voltage to be corresponding to the gain of the error amplifier, and the error amplifier is usually specified as a line and load adjustment.
The current mode controller maintains a fixed error signal under the line voltage deviation of the line, because the slope of the slope signal changes, but it still rely on changes in the error signal to obtain the load deviation. The V2TM control method is to maintain a fixed error signal for lines and load changes, because the slope signal is affected by the line and load.
Constant shutdown time
In order to maximize the transient response, CS5166 uses a constant closing time method to control the rate of output pulse. During the normal operation period, the disconnection time of the high -voltage side switch is terminated after a fixed time set by the control capacitor. In order to keep the adjustment, the V2TM control circuit changes the connection time. The PWM comparator monitor the output voltage slope and terminate the switch connection time.
Constant closureThere are many advantages in time. When responding to the transient conditions, the switching duty cycle can be adjusted from 0 to 100%by pulse. 0%and 100%duty cycle can be maintained for a long time to respond to the load or line transient. Avoid PWM slope compensation to avoid secondary resonance oscillations under the high occupation ratio.
The power -on time is limited by the internal 30μs (typical) timer, which reduces the pressure on the power component to the maximum.
A programble output
CS5166 aims to provide two methods to program the output voltage of the power supply. A five -bit plate module converter (DAC) is used to program the output voltage within two different areas.
Available output
CS5166 design to provide two methods for providing two programming power supply output voltage. A five -bit plate module converter (DAC) is used to program the output voltage within two different areas.
The first range is 2.125V to 3.525V, the step length is 100mV, the second range is 1.325V to 2.075V, and the step length is 50mV, depending on the digital input code. If all five are kept opening, CS5166 enters the adjustment mode. In the adjustment mode, the designer can select any output voltage by feeding the VFB pin by using a resistor division to the VFB pins like a traditional controller. Designed to meet Intel Pentium or CS5166 specifications.
Start
Until the voltage on the VCC power pins exceeds 3.95V monitor threshold, soft startup and grid lection foot remain at a low level. Fault lock reset (non -failure state). The output of the error amplifier (compensation) was pulled to 1V. When the VCC pin exceeds the threshold of the monitor, the door (H) output is activated, and the soft startup capacitor starts charging. The door (H) output will be kept open and the NFET switch will be enabled until the PWM comparator or the maximum connection time timer is terminated.
If the output voltage of the regulator exceeds the maximum connection time before reaching the 1V level, the pulse is terminated. During the extended closing time, the gate (H) pin drives low level, and the gate (L) pin drives high level. At this time, the timeout of the timeout timer is about the maximum connection time, which generates a 50%duty ratio. The gate (L) pins will then drive low levels, and the gate (H) pin will drive high levels and repeat the cycle.
When the output voltage of the regulator reaches the 1V level sent by the compensation pins, the adjustment has been realized, and the normal shutdown time will occur. The PWM comparator terminal is used for switching time, and the shutdown time is set by COFF to set the capacitor. The V2TM control loop will adjust the switch to occupy the duty ratio as needed to ensure the output of the regulator output voltage tracking error.
Soft startup and compensation capacitors will charging to the final level, providing controlling the control of the regulator output. The opening time of the regulator is compensated capacitorsCharging until its final value is determined. Its voltage is soft -start compensation clamp and the voltage restrictions on the softening feet.
During the normal operation period, the shutdown time is constant, which is set by the COFF capacitor settings Essence The power -on time is adjusted by the V2TM control loop to keep the adjustment. This will cause the regulator to switch the frequency, occupy ratio and output ripples with the load and line output voltage ripples, which will be determined by the electromotone's carding current and the ESR of the output capacitor (see Figure 6 and Figure 7). 
Instant response
CS5166 V2TM control loop's 150ns reaction time provides unprecedented transient response to changes in the input voltage or output current, Essence Provide a pulse and a pulse adjustment to the duty occupation ratio to quickly increase the electricer current to the required level. Because the current of the inductors cannot be changed instantly, the output capacitor is maintained during the time when the electrone current needs to be converted. 
By the function called adaptive voltage positioning , the overall load transient response was further improved. This technology pre -positions the voltage of the output capacitor to reduce the total output voltage offset during the load change.
The reference voltage that keeps the tolerance of 1%allows an error amplifier to reach+25mv high without affecting DC accuracy. A drooping resistor is implemented through a PC board trajectory to connect error current feedback pins (VFB) to the output capacitor and load, and carry output current. In the case of no load, there is no DC voltage drop on the resistance, which generates the output voltage of the tracking error current, including+25mv offset. When the full load current is transported, 50mV voltage drops are generated on the resistance. This causes the output voltage to offset 25 millivolves low.
The result of an adaptive voltage positioning is that before reaching the output voltage specification limit, it provides additional margin for the load transient state. When the load current suddenly increases from its minimum level, the output capacitor is pre -positioned at+25mv. Instead, when the load current suddenly decreases from its maximum level, the output capacitor is pre-positioned to -25mV (see Figure 8, 9, and 10). In order to obtain the best transient response, some combinations of high -frequency and large -capacity output capacitors are usually used.
If the maximum connection time is exceeded when the response load current suddenly increases, the normal disconnection time will occur to prevent the output sensor from saturation.
Power sorting
CS5166 provides inherent protection and is not affected by unfarished start -up conditions. Regardless What is the order. The turning conversion rate of 12V and 5V power supply can be changed in a large range without affecting the output voltage or caused by the boost regulatorNegative Effects. 
Protection and surveillance function 
provides a small interference mode restriction function with losses, which only needs to softly start the capacitor to achieve. CS5166 provides over -current protection by using an internal current detection comparator and a speed reduction resistor sensor current. The comparator compares this voltage drop with the internal reference voltage of 76MV (typical).
If the voltage on the speed reduction resistor drops exceeds this threshold, the current influenza response comparator allows the fault locks. This will cause the regulator to stop switching. In this case, CS5166 keeps off within the time when the soft startup capacitor is slowly discharged through the 2μA current source until it reaches its lower 0.7V threshold.
At this time, the regulator tries to restart normally by sending short grid pulses to two FETs. The CS5166 will initially run at a 50%duty cycle, while the soft startup capacitor is charged with a charging current of 60 μA. When the soft startup capacitor is charged to the upper limit of 2.7V, the goalkeeper is opened. Under the overload conditions, the soft -start charging current ratio sets the pulse duty cycle (2 μA/60 μA u003d 3.3%). When the VFB is less than 1V, the actual duty cycle is half of the extension of the closing time mode (1.65%). The soft start of the interrupt pulse is 3ms. When the failure is detected, the duty cycle is repeated, otherwise it will return to normal operation.
Due to the continuous existence of over -current, the protection scheme can minimize the thermal stress of the regulator component, input power and PC board traces. After the overload is lifted, the fault lock is cleared, allowing normal operations. The current limits can be adjusted through the external resistor to provide users with the flexibility of the current limit setting point.
Overvoltage protection
Overvoltage protection (OVP) is the result of the normal operation of the V2TM control topology, no additional external components are required. The control circuit responds to the overvoltage conditions in the 100ns, causing the top MOSFET to turn off, thereby breaking the regulator with its input voltage. The bottom MOSFET was then activated to generate a pry pole action to restrain the output voltage and prevent damage to the load (see Figures 13 and 14). The regulator will keep this state until the overvoltage is stopped or the input voltage is pulled down. The bottom FET and board tracking must be correctly designed to achieve the OVP function. If you need a dedicated OVP output, you can use the circuit in Figure 15 to implement. In this figure, if the output voltage (VCORE) exceeds 20%of the voltage set by a specific DAC code, the OVP signal will become higher (overvoltage conditions) if PWRGD is lower. The voltage conditions are also required to exist within the PWRGD delay time that activates the OVP signal. The resistance value displayed in Figure 15 is suitable for VDAC u003d+2.8V (DAC u003d 10111).VOVP (overvoltage checkpoint) can be used to use the following formula:
Good power circuit
Good pins (123] Good pins ( Point 13) is an open -circuit collector signal that meets the TTL DC specification. When the output voltage of the regulator usually exceeds ± 8.5%of the nominal output voltage, it is pulled up by the outside and lowered (below 0.3V). The maximum output voltage deviation of the previously lowered power is ± 12%.
FIG. 17 shows the relationship between the voltage voltage output voltage VFB and good power signals. In order to prevent Power Good from interrupting the CPU unnecessaryly, CS5166 has a built -in delay to prevent the noise at the VFB pin from switching to Power Good. The internal time delay design is about 75 microseconds when the power consumption is good, and the recovery is 65 microseconds. This makes the good power signal is completely unspealable for the irregular conditions that last less than the built -in delay (see Figure 18).
Therefore, before the state of good power signal changes, the output voltage is required to reach at least the level or adjust the level at least within the built -in delay time.
The opening/closing control of the regulator can be achieved by adding two additional separate elements (see Figure 19). The circuit runs the Iseense pin and runs down by pulling the soft -starting pin, and the Iseense pin is low, and the simulation current limit conditions are run.
CS5166 Anti -pressure regulator can be used with various external power components to optimize the cost and performance of specific design. The following information can be used as a general guide to help choose them.
NFET power transistor
Logical electric flat and standard field effects of the standard field can be used. The reference design is a grid drive from the 12V power supply. The 12V power supply is usually available in most computer systems and uses a logical grade FET. The charge pump can be easily realized as a system that only supports 5V. Multiple field effect transistors can be connected in parallel to reduce loss, improve efficiency and heat management.
The voltage applied to the FET gate depends on the application circuit used. When you are in a low state, the output of the upper and lower grille drives is driven to the ground 1.5V, and the 2V of each biased power supply is driven when high state. In fact, the FET goalkeeper is driven by one by one due to the overching caused by the capacitance load caused by the FET gate to the controller IC. For typical applications using VCC u003d 12V and 5V as a regulator output current source, the following grille drivers are provided:
[see Figure 20).
The most important aspect of the field effect tube performance is RDSON, which affects the efficiency and FET thermal management requirements of the regulator.
The power consumed by MOSFET can be estimated as follows:
Switch MOSFET: 
Synchronous MOSFET:
Turn off the time capacitor
COFF timer capacitor settings adjustment time:
The above -mentioned duty cycle ratio can also be available. In the calculation regulator switch frequency and select COFF timer capacitor: 
can connect the Schottky diode with the synchronous field effects crystal tube in order to turn the inductor current during the transistor of the switch field to improve the efficiency. The CS5166 reference circuit does not use the device due to its excellent design. Instead, the body diode of the synchronous field effect of the synchronous field effect is used to reduce costs and transmit inductor current. For the design of work around 200kHz, the combination of low non -overlapping time with Schottky positive recovery time may make the advantages of the device not worth additional costs. The power loss generated by the body diode in the synchronous MOSFET can be estimated by the following equal formula:
power u003d vbd × Iload × conduction time × switching frequency, where the VBD u003d MOSFET body diode is dropped.
For CS5166 demonstration board: power u003d 1.6V × 14.2A × 100ns × 200kHz u003d 0.45W
The drooping resistor used for adaptive voltage positioning
The adaptive voltage positioning is used to help maintain the output voltage within the specification range during the load transient state. In order to achieve an adaptive voltage positioning, a drooping resistor must be connected between the output induction, the output capacitor and the load. The resistor carries the full load current, and this resistance should be selected to meet DC and exchange tolerance restrictions. The embedded PC tracking resistance has a significant advantage of approaching zero. However, this droopingThere are three reasons for changes in resistors: 1) change of sheet resistivity causes the thickness of the PCB layer. 2) L/W do not match, and 3) temperature changes.
1) thin piece resistivity
For copper of 1 ounce, the thickness changes are usually 1.15 dense to 1.35 dense ear. Therefore, the error caused by the resistance rate of the sheet is:
2) L/W does not match
The change of the PCB manufacturing process is caused by the PCB manufacturing process Change control, these changes will affect the drooping resistor. The error caused by L/W is usually 1%.
3) Thermal factors
Due to the I2 × R power loss, the surface temperature of the sag resistor will increase, resulting in an increase in resistance. In addition, according to the following formulas, changes in the ambient temperature will help increase the resistance:
In the formula: the resistance at R20 u003d 20 ° C
T u003d working temperature;
R u003d The expected resistance value temperature T u003d 50 ° C,%R change u003d 12%
Dynamic resistance pigraphytic chip resistance resistance Tolerance caused by changes: 16%
L/W error: 1%
Trip tolerance caused by temperature: 12%
The chief of the drooping resistor : 29%
Example: For 300MHz Pentium u0026#174; II, the DC accuracy specification is 2.74 u0026 lt; VCC (core) u0026 lt; 2.9V, and the exchanges are 2.67V u0026 LT; VCC (VCC (VCC (VCC ( Core) u0026 lt; 2.93V. CS5166 DAC output voltage is+2.796v u0026 lt; VDAC u0026 LT;+2.853V. In order not to exceed the DC accuracy specification, the voltage reduction generated on the resistance must be calculated as follows:
In the case of CS5166's DAC accuracy of 1%, the reference voltage of the internal error amplifier is fine -tuned to make The output voltage reaches 25mv when the load is empty. In the case of no load, there is no DC voltage drop on the resistance, generating an output voltage of a tracking error placing output voltage, including offset. When the full load current is transported, the -43MV voltage drop will be generated on the resistance. Therefore, before the load is turned on, the regulator output is positioned in advance at a position of 25 millivoltage higher than the nominal output voltage. The total voltage caused by load steps is u0026#8710; V-25MV, and the deviation from the nominal output voltage is 25mV, which is compared to the deviation of the drop-to-reduction resistorLittle 25 MV. Similarly, when the load is turned off, the regulator output is positioned in advance at a position below the nominal voltage 18mV. The total voltage increase caused by the load shutdown is u0026#8710; V-18MV, the deviation of the bias of the nominal output voltage is 18mV, and the deviation of the bias when there is no resistance is 18mv. This is because the output capacitor is charged in advance before the load is connected to the value of 25 millivolozoa or lower than the rated output voltage 18 millival (see Figure 8).
Obviously, the larger the voltage drop on the pressure reduction (the larger the resistance), the worse the DC and the load adjustment, but the better the communication transient response.
The current limit setting value calculation 
We choose the value of the current sensing element (embedded PCB tracking) as the minimum current limit setting value:
This will cause internal current detection comparator to detect overload.
From the current detection data segment, the setting value of the rated current limit 
Therefore,
] Therefore, the internal current detection comparator passed 3M u0026#8486; embedded PCB trajectory to detect the load current range of overload conditions: 14.2A u0026 LT; ICL u0026 LT; 51.6A, and 25.3A as the nominal overload conditions.
Some applications may need to use two additional filter components, a 510 u0026#8486; the resistor connects with the Isense pin, and a 0.1 μF capacitor is attracted in Isense and VFB leadBetween feet. These are required for the correct current limit operation, and the resistance value depends on the layout. The calculation of this series resistor affects the setting value of the current limit, and it must be considered when determining the valid current limit. 
NSE × ifiseb (vertical strength × vertical strength)
formula, VTRIP u003d voltage on the drop resistor of the Isense comparator
vth u003d internal isnse Comparing threshold
Isense u003d Isense bias current
risense u003d Isense pin 510 u0026#8486; filter resistance
RFB u003d VFB pin 3.3K filter resistance
IFB u003d VFB bias current
When using RISENSE, the minimum current resistance required for the current limit (resistor) voltage drop
The rated current detection resistor (resistor) uses the voltage drop required for current limit when using RISENSE
When using Risense, the maximum current fluid resistance required for current limit ( During the drop resistance) voltage drop 
Then calculate the value of the RSENSE (current detection PCB tracking): 
Make the internal inside the internal The load current range of the current influenza comparator detects overload conditions is as follows: 
Therefore,
Maximum current limit setting value
Therefore,
Therefore, internal current leads to internal current The detector of the detector through 3M u0026#8486; embedded PCB trajectory to detect the load current range of overload conditions is: 14.2A u0026 LT; ICL 60A, 28.6A as the nominal overload conditions.
The design rules of the drooping resistor
The basic equation of the buried resistor is:
or 
a u003d w × t u003d horizontal cross-sectional area
ρ u003d copper resistivity (μ u0026#8486; -mil)
l u003d length (dense ear)
W u003d width (mils)
t u003d thickness (mils)
For mostDifferent polychloride, one ounce of copper thickness T is 35 μm (1.37 mils). 8 u003d 717.86μ u0026#8486;
For the Pentium II load of 14.2A, the resistance required t