A3PE3000L-1FG484I FEATURES AND BENEFITS Tested and Qualified Military Temperature? Each device tested at –55°C to 125°C? Advanced and Professional I/O??????················································ 700 Mbps DDR with I/OS1 support .2 V, 1.5 V, 1.8 V, 2.5 V LV and 3.3 V mixed voltage operation? Up to 8 groups of selectable I/O voltages per chip Single-ended I/O standards: LVTTL, LVCMOS 3.3 V/2.5 V/ 1.8 V/1.5 V/1.2 V, 3.3 V PCI/3.3 V PCI-X and LVCMOS 2.5 V/5.0 V input? Differential I/O standards: LVPECL, LVDS, BLVDS and M-LVDS Voltage Reference I/O standard: GTL+ 2.5 V/3.3 V, GTL2.5 V/3.3 V, HSTL class I and II, SSTL2 class I and II, SSTL3 class I and II (A3PE3000L only) input and output I/O registers, and enable path switching and Cold backup I/O Programmable output slew rate and drive strength Programmable input delay (A3PE3000L only) Schmitt trigger option on single-ended input (A3PE3000L) Weak pull-up/down IEEE 1149.1 (JTAG) boundary scan test leads Foot Compatible Package Cross Military Proasic™ 3elfamilyfirm error immune?not susceptible to neutron induced configuration: LoSoS-Power: Sharp reduction of dynamic and static power: 1.2 V to 1.5 V Core and I/O voltage support low power consumption, FLASH ＊Low power consumption in freeze mode allows instant entry/exit of low power FLASH FRIEZMODEDYO: Supports single voltage system operation Low impedance switching /O programmable flash technology ) and PLL? Six CCC modules, one with integrated PLL (Proasic3), all with integrated PLL (Proasic3el)? Configurable phase shift, multiply/divide, delay capability, and external feedback? Wide input frequency range 1.5 MHz to 250MHz (1.2V system) and 350MHz (1.5V system) High performance? 350MHz (1.5V system) and 250MHz (1.2V system) System performance? 3.3V, 66MHz, 66-bit PCI (1.5V system) system) and 66 MHz, 32-bit PCI (1.2 volt system) SRAM and FIFOS? Variable aspect ratio 4,608-bit RAM blocks (×1, ×2, ×4, ×9, and ×18 available organizations)? True of dual-port SRAM (except ×18)? SRAM and FIFO configuration for 24 simultaneous operations: –250 MHz: for 1.2 V systems –350 MHz: for 1.5 V systems? ?ARM Cortex?-M1软处理器，可用于或不用于调试A3P1000M1A3P10001M24，576144321kyes1184154pq20fg144a3pe3000lm1a3pe3000l3m75264504111kyes6188620in系统编程（isp）和安全?通过jtag（符合ieee 1532）使用片上128位高级加密标准（aes）解密保护isp?flashlock? To protect fpga content High performance routing hierarchy? Segmentation, hierarchical routing and clocking fabric? High performance, low skew global network? Architecture supports ultra-high utilization

Note 1. When considering migrating your design to low-density or high-density devices, please refer to the packaging section of the datasheet to ensure you meet design and board migration requirements. Each differential I/O pair used reduces the number of single-ended I/Os available by 2.3. "G" indicates RoHS compliant packaging. See "Military Item 3/EL Ordering Information" on page three for the location of part number "G". For A3PE3000L devices, the use of certain I/O standards is subject to the following restrictions: – SSTL3 (i) and (ii): up to 40 I/Os per North Bank or South Bank – LVPECL/GTL+3.3 V/GTL 3.3 V: each Up to 48 I/Os per North or South Shore – SSTL2 (i) and (ii)/GTL+2.5 V/GTL 2.5 V: Up to 72 I/Os per North or South Shore. When using the flash*freeze pin to enable flash*freeze mode directly instead of as regular I/O, the number of single-ended user I/Os available is reduced by one.

1 – Overview of Military Proasic3/EL Device Family Overview Military Proasic3/EL series Actel Flash FPGAs significantly reduce dynamic power consumption by 40% and static power consumption by 50%. These power savings are combined with performance, density, true single-chip, 1.2V to 1.5V core and I/O operation, reprogrammability, and advanced features. Actel's proven Flash* Freeze technology enables users of military Proasic3el devices to instantly power down dynamic power and switch the device to static mode without shutting down the clock. or power supply, and maintain the internal state of the device. This greatly simplifies power management. In addition, optimized software tools using power-driven layouts provide continuous button power reduction. Non-volatile flash technology provides a secure, low-power, single-chip solution for military Proasic3/EL devices called Real Time Power On (LAPU). Military PROASIC3/EL devices offer significant dynamic power savings, giving FPGA users the flexibility to combine low power and high performance. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. Military PRASIC3/EL devices provide 1K bits of on-chip, programmable, non-volatile flash memory. And a clock conditioning circuit (ccc) based on an integrated phase-locked loop (pll). Military proasic3/el devices support devices ranging from 600k system gates to 3 million system gates, with 504 kbits of true dual port SRAM and 620 user i/os. The m1 military proasic3/el device supports the high-performance 32-bit cortex-m1 processor developed by arm for implementation in fpgas. arm cortex-m1 is a soft processor, fully implemented in fpga structure. It has a three-stage pipeline that provides a good balance between low power consumption and speed when implemented in the M1 Military Proasic3/EL device. The processor runs the armv6-m instruction set, has a configurable nested interrupt controller, and can be implemented with or without debug blocks. ARM Cortex-M1 is freely available from ACTEL for M1 military Proasic3/elfpgas. ARM-enabled devices have ACTEL order numbers starting with M1 and do not support decryption. Flash*Freeze Technology? Military Proasic3el devices offer ACTEL's proven Flash*Freeze Technology, allowing instantaneous switching from active to inactive. When flash* freeze mode is activated, the military proasic3el device enters a static state while preserving the contents of registers and sram. Power saving, no need for additional external components to shut down/shutdown the OS or clock. Flash*freeze technology combined with in-system programmability enables users to quickly and easily upgrade and update their designs in the final stages of field production. The ability of military PROASIC3EL devices to support a 1.2 V core voltage allows for greater power reduction, which results in lower overall system power. When a military PROASIC3EL device enters FLASH freeze mode, the device automatically turns off clocks and inputs to the FPGA core; when the device exits Flash* freeze mode, all activity and data are preserved. The availability of low-power modes, combined with a reprogrammable single-chip, single-voltage solution, makes military Proasic3el devices suitable for low-power data transmission and operation in military temperature applications where available power may be limited (for example, in battery-operated equipment ); or where heat dissipation may be limited (e.g. in an enclosure without forced cooling)

Military Proasic3/EL Device Family Overview Flash Advantages Low Power Actel Flash-based FPGAs The Military Proasic3el family offers low power advantages that, when combined with high performance, enable designers to use a reprogrammable single chip to make power smarts select, and power up the device. Military Proasic3el devices provide 40% dynamic power and 50% static power savings by reducing the core operating voltage to 1.2V. In addition, the Power Driven Layout (PDL) feature in the Libero® Integrated Design Environment (IDE) provides up to 30% additional power reduction. Using Flash*Freeze technology, military Proasic3el devices retain device SRAM and logic, minimizing dynamic power without stopping clocks or power supplies. Combining these features provides a low-power, feature-rich and high-performance solution. Security non-volatile, Flash-based military Proasic3/EL devices do not need a boot prom, so there is an unbreakable external bitstream that can be easily replicated. Military proasic3/el devices have built-in flashlock, which, with no external overhead, offers a unique combination of reprogrammability and design security, an advantage that only FPGAs with non-volatile flash programming can provide. Military proasic3/el devices use 128-bit flash-based locks and individual AES keys to protect programmed intellectual property and configuration data. Additionally, all flashrom data in military proasic3/el devices can be encrypted using the industry-leading aes-128 (fips192) bit block cipher encryption standard prior to loading. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000, replacing the 1977 DES standard. Military proasic3/eldevices have a built-in AES decryption engine and a flash-based AES key, making them the most comprehensive programmable logic device security solution available today. AES-secured military proasic3/eldevices allow secure, remote field updates over public networks such as the internet and ensure that valuable IPs do not fall into the hands of system overbuilders, system cloners and IP thieves. While secure design verification is possible, the contents of programmed devices cannot be read back. The security built into the FPGA fabric is an inherent component of the military proasic3/el family. Flash cells are located under seven metal layers, and many device design and layout techniques have been used to make intrusion attacks extremely difficult. Military proasic3/elfamily with flashlock and aes security, high resistance to invasive and non-invasive attacks. Your precious IP is protected and secure, enabling remote ISPs. Simple proasic3/el devices provide the most impenetrable security for programmable logic designs, and single-chip flash-based FPGAs store their configuration information in the on-chip flash unit. Once programmed, configuration data is an inherent part of the FPGA fabric and no external configuration data needs to be loaded when the system is powered up (unlike SRAM-based FPGAs). Therefore, flash-based military proasic3/el-fpgas do not require system configuration components such as eeprom or controllers to load device configuration data. This reduces bill of materials cost and printed circuit board area, improving safety and system reliability. Flash-based real-time military item 3/EL devices support level 0 of the LAPU taxonomy. This feature helps with system component initialization, performing critical tasks before the processor wakes up, the setup and configuration of memory blocks, clock generation, and bus activity management. The lapu feature of flash-based military proasic3/el devices greatly simplifies overall system design, reduces overall system cost, and typically does not require cpld and clock generation plls. Additionally, glitches and failures in system power do not corrupt the flash configuration of MILITARYPROASIC3/EL devices, and unlike SRAM-based FPGAs, the device does not have to be reloaded when system power is restored. This enables configuration proms, expensive voltage monitors, browser detection and clock generator devices to be reduced or completely eliminated from the PCB design. Flash-based military proasic3/el device simplifies overall system design and

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