Features

gt; 400 mbps (200 mHz) exchange rate

Pattishment of the PCB layout

300 PS typical difference deviation

400 PS maximum differential deviation

1.7NS maximum transmission delay

3.3V power supply design [123 [123 ]

± 350 mv Differential signal

Low -power consumption (static 3.3 volt at 13 MW)

5-V LVDS receiver for interoperability

High impedance of LVDS output during power off

compliance with TIA/EIA-644 LVDS standard

] industrial work temperature range ( 40 ° C to+85 ° C)

surface sticker SOIC and thin TSSOP packaging

Application

]

Multifunctional Printer

LVDS -LVCMOS translation

Instructions

DS90LV047A The device is four The core CMOS flows through the differential line driver, designed for the application of ultra -low power consumption and high data rates. The device uses a low -voltage differential signal (LVDS) technology to support the data rate of more than 400 Mbps (200 MHz).

DS90LV047A accepts low -voltage TTL/CMOS input levels and converts it to low -voltage (350 millival) differential output signals. In addition, the driver supports the triangle function, which can be used to disable the output level and disable the load current, thereby reducing the device to a typical 13 MW ultra -low idle power state. DS90LV047A has a circulating pin for PCB layout.

EN and EN*input are combined with with and control the three -state output. Enable all four drivers is universal. DS90LV047A and the accompanying line receiver (DS90LV048A) provide a new alternative to high -power PSUedo ECL devices for high -speed point interface applications.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Function Figure

Typical feature

Parameter measurement information

Detailed instructions

Overview

LVDS driver and receiver are mainly used for simple point -to -point configuration, as shown in Figure 23. This configuration provides a clean signaling environment for the fast edge rate of the drive. The receiver is connected to the driver through a balanced medium. This medium can be a standard twisted cable, parallel parallel pair of cables or simple PCB traces. Generally, the characteristics of the media's characteristics are within the range of 100Ω. The terminal resistance is 100Ω (selected to match the medium), and as close to the receiver input pin as much as possible. The terminal resistor converts the drive output current (current mode) to the voltage detected by the receiver. Other configurations are possible, such as multi -receiver configuration, but it is necessary to consider the impact of midflow connectors, cable heads and other impedance discontinuousness, as well as ground movement, noise capacity limit, and the effects of the total load.

DS90LV047A Differential Circuit Drive is a balanced current source design. Generally speaking, the current mode drive has high output impedance and provides constant current for a series of loads (on the other hand, the voltage mode drive provides constant voltage for a series of loads). The current is switched in one direction to generate a logical state, and switch between another direction to generate another logical state. The output current is often 3.1 mAh, the minimum is 2.5 mAh, and the maximum is 4.5 mAh. The current drive (as described above) requires the termination signal with the resistance end and completes the loop, as shown in Figure 23. Configurations that are not allowed to use communication or unnecessary connection. 3.1 mia circuit current forms a 310 millivoltage differential voltage on the 100Ω terminal resistor. The minimum motion noise margin detected by the receiver is 250 millivolo (driving signal minus the receiver threshold (250 millivolta — 100 millivol to 100 millivolta 100 millivolta 150 millivolves). As shown in Figure 22, the signal center is located near+1.2V (drive offset, VOS).

Note: The steady -state voltage (VSS) peak is the differential voltage (VOD) Two times, usually 620 mv.

The current mode drive is a substantial benefit to the voltage mode drive (such as the RS-422 drive). -422 Voltage mode Drives grow from 20 Mixh to 50 Might in most cases. This is caused by the overlapping current flowing between the orbits of the device when the internal door is switched. Switch a fixed current without any substantial overlap current. This is similar to some ECL and PECL devices, but there is no heavy static ICC requirements for ECL/PECL design.ECL. The communication specification of the driver is 10 times more than other existing RS-422 drivers.

The trio function allows the disabled drive output, so as to obtain a lower power state when not required to transmit data.

Function box diagram

Function description

lvds failure protection

Discussion in this section discusses lvds interconnect fault safety partial partial partial partial partial part Common problems, especially the DS90LV047A driver output and DS90LV048A receiver input.

LVDS receiver is a high -gain, high -speed device, which enlarge a small differential signal (20mv) to the CMOS logic level. Due to the high gain and strict threshold of the receiver, please pay attention to prevent noise from appearing as a valid signal.

The internal fault safety circuit design of the receiver is used to generate or absorb a small amount of current, and provides fault protection for the input of floating, end -connecting or short -circuit receivers (a stable state of high output voltage).

1. Open the input pin: DS90LV048A is a four -way receiver equipment. If the application only needs 1, 2 or 3 receivers, the unused channel input must be opened. Do not input the unused receiver to the ground or any other voltage. The input is biased from the internal high -value upper and drop -down resistance to set the output to a high state. This internal circuit ensures the high and stable output state of the open input.

2. Termination input: or when the LV907A power supply is disconnected, if a DS907A cable is disconnected, or when the LV907A drive is disconnected, or the LV907A power supply is disconnected The-ω input terminal connects the resistor. Unplug the cable will become a floating antenna. If the cable receives a differential noise of more than 10 millions, the receiver may regard the noise as a valid signal and switch. In order to ensure that any noise is considered a co -mode rather than a differential, a balanced interconnection must be used. The twisted cable has a better balance than a flat band -shaped cable.

3. Input short circuit: If the receiver inputs a short circuit failure, which will cause the 0-V differential input voltage, the receiver output will remain in high state. Within the scope of the co -mocofea (GND to 2.4 V), short -circuit input fault protection is not supported. It is supported only when the input is short -circuited without applying an external co -mode voltage.

External low -value upper pull -up resistance and drop -down resistance (for stronger bias) can be used to improve fault safety when there is a higher noise level. The pull-up resistance and drop-down resistance should be within the range of 5-kΩ to 15-kΩ to minimize the load and waveform distortion of the driver. The co -mode bias point should be set to about 1.2 V (less than 1.75 V) to be compatible with internal circuits.

Device function mode

Table 1 lists the functional mode of DS90LV047A.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification. TI does not guarantee its accuracy Or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

DS90LV047A has a circulating pin, allowing simple PCB layout. The LVDS signal on one side of the device can easily match the electrical length of the trace line between the driver and the receiver, and allow these traces to approach the coupling noise as the co -mode. Noise isolation is implemented on the device side and TTL signal through the LVDS signal.

Typical application

Design requirements

When using LVDS devices, be sure Instrument. All components of the transmission medium shall have a matching difference of about 100Ω. They should not introduce major impedance incompleteness.

Balanced cables (for example, twisted lines) are usually better reduced than unbalanced cables (band -like cables). Due to the field of the field, balanced cables often produce less electromagnetic interference, and it is easy to pick up electromagnetic radiation as a co -mode (not a differential mode) noise. The noise is rejected by the LVDS receiver.

For cable distance less than 0.5 m, most cables can work effectively. For the distance of 0.5 m≤d ≤ 10 m, the CAT5 (5) twisted wire cable works well, it is easy to obtain, and the price is relatively cheap.

Detailed design program

Detect LVDS transmission line

always uses high impedance ( gt; 100kΩ), low -capacitor ( lt; 2PF) oscilloscope probe, and the range is wide (1GHz). Inappropriate detection will produce the result of deception.

Data rate and cable length curve test program

Pseudo -random sequence (PRBS) of 29 HFS9009 in the function generator (Tektronix), and pass 50Ω The cable and SMB connector are connected to the driver input. Use Tektronix 11801B to detect the results of the results and perform differential measurements at the input terminal of the receiver. A 100Ω resistor is used to connect this pair of cables at the remote end of the cable. At the remote end of the cable, measure at the input end of the receiver and use it for the jitter analysis of the figure (Figure 16). The frequency of the input signal increases until the measurement jitter of the length of the specific cable is measured (TTCS) is equal to 20%of the unit interval (TTUI). Starting from many system design, 20%jitter is a reasonable starting point. The data used is NRZ. Measure the jitter under the 0-V differential voltage of the differential eye diagram. You can use the new DS90LV047-048AEVM to evaluate DS90LV047A and DS90LV048A.

FIG. 24 shows a very good typical performance, which can be used as a design guide for data rate and cable length. Increasing jittering percentage will increase the curve separately, so that the device is transmitted faster on the length of the longer cable. This relaxes the glittering tolerance of the system and allows more jitter to enter the system, which may reduce the reliability and efficiency of the system. Alternatively, reducing the shake percentage comparison system has the opposite effect. According to the above signal quality standards, the area under the curve is considered a safe operating area. For more information about the eye map test, see the AN-808long transmission line and data signal quality (SNLA028).

Application curve

Power suggestion

Although DS90LV047A consumes very small power in a static state. At a higher switch frequency, a dynamic current component exists, which increases the overall power consumption. The DS90LV047A power connection must consume this additional current consumption of the maximum power requirements.

Layout

layout guide

at least 4 PCB layers (from top to bottom); LVDS signals, grounding, power supply, TTL signals.

isolate the TTL signal from LVDS signals, otherwise TTL may be coupled to the LVDS line. It is best to put the TTL and LVDS signals on different layers, and these layers are isolated from the power/horizon.

Make the drive and receiver as close to the (LVDS port side) connector as possible.

Power supply decoupling advice

Winging capacitors must be used on the power pins. Using high-frequency ceramics (recommended on the surface with surface stickers) at the power pins (recommended) 0.1-μF and 0.001-μF capacitors, the minimum capacitor is closest to the device power supply foot. The additional dispersing capacitors on the printing circuit board improved the decoupling capacity. Multi -pores must be used to connect to the power supply plane. The inlet point between the power supply between the printing circuit board and the grounding point between the power supply and the ground must be connected to 10-μF (35-V) or a larger solid pillar capacitor.

Micro -score record

Use the controlled impedance trajectory of differential impedance matching with the transmission medium (ie, cable) and terminal resistance. Once the difference is left to the IC, they should be as close as possible (the length of the short -cut line must be less than 10 mm). This helps eliminate reflexes and ensure noise as a co -mode coupling. In fact, we have seen that it is 1 mm apartThe differential signal is much smaller than the noise of radiation of 3 mm distance, because the magnetic field is much better on the recorded records that are closer. In addition, the noise generated on the differential lines is more likely to be manifested as a co -mode rejected by the receiver.

The electrical length between the matching lines to reduce the deviation. The deviation between a pair of signals means that the phase difference between the signals will destroy the differential signal and the magnetic field of the EMI to offset the advantage.

Note: The speed of communication, v c/er, where C (light speed) 0.2997mm/PS or 0.0118 inches/second.

For differential records, do not just rely on the automatic wiring function. Check the size to match the difference in the difference and provide isolation for the differential lines. Try to reduce the perforated and other discontinuousness on the line.

Avoid a 90 ° turn (this will cause impedance discontinuous). Use an arc or 45 ° slope.

In a pair of records, the distance between the two records must be minimized to keep the receiver's co -mode suppression. On the printing circuit board, this distance must be kept constant to avoid the discontinuousness of differential impedance. Mild violations are allowed at the connection point.

Termination

Use terminal resistance that matches the most impedance or transmission line. The resistor must be between 90Ω and 130Ω. Remember, the current output requires the terminal resistance to generate differential voltage. LVDS does not work without the resistance end. Under normal circumstances, it is enough to connect a resistor at the receiver.

1%to 2%resistance on the surface is the best. The distance from the PCB storage, component lead, and the distance from the terminal to the receiver must be minimized. The distance between the terminal and the receiver should be less than 10 mm (maximum 12 mm).

layout example