A complete interface between LNB

I2CTM bus

Built -in DC/DC controller

Single 12V power operation and

High efficiency (typical example . 94%(750 mAh)

Two optional output current

Limit (450ma/750ma)

both conforms Output voltage

Specification

Precise built -in 22kHz tone

oscillator is suitable for wide acceptance

standard

fast oscillator start

]

DISEQCTM encoding

Built -in 22kHz tone detector

Support two -way Diseqctm2.0

Semi -low rear adjustment and low power consumption: typical. At 125mA, 0.56W

Two output pins suitable for bypass

output R-L filter to avoid any

tone distortion (R-L filter based on

Diseqc 2.0 specification, see the application circuit page number. (5)

Cable length digital compensation

overload and ultra -temperature

Internal protection

overload And over-temperature I2C

Diagnostic position

LNB short circuit SOA protection

Bringing I2C diagnostic position +/- 4KV ESD input capacity difference/output power supply feet

] Explanation

It is used to simulate and digital satellite set-top box receiver/satellite TV, TV/PC card,

lnbh21

is a single-chip regulator and interface IC, which is installed on the power SO-20 Above, especially the design to provide 13/18V power supply and send a 22kHz audio signal antenna or a multi -function switch to LNB. Design simple I2CTM standard interface.

Typical application circuit

Diseqc 1.x application circuit, output current lt; 450 ma

1 . The filter recommended by EUTELSAT to achieve DISEQCTM 2.0 (see Diseqctm on page 8). If the two -way Diseqctm 2.0 is not implemented, you can use C8 and D4 to delete it.

2. If not if not Use, don't let these sales float.

3. Do your bestIt may be close to the related pins for welding. -C8 and D3,4 are only used to protect the output pins during the high -speed voltage conversion period without any negative voltage peak.

Application information

This integrated circuit has a built -in DC/DC boost controller. From a power supply of 8 to 15V, it generates linear rear regulator to work with minimum dispersion power to work Voltage (VUP) 1.65W typical value. @750mA load (linear regulator pressure drop is kept inside: vup-vo 2.2V typical value). When the VCC provided by Andang is lower than the fixed voltage, the underwriter locking circuit will enable the entire circuit to fail the threshold (usually 6.7V). Internal 22kHz audio generator can control real -time Diseqctm data coding (*) through the I2CTM interface or special pipe foot (DSQin). When the 10 (tone is enabled) I2C bit is set to high -electricity. A, no matter what the logic state of the DSQIN pin, the output end will generate a continuous 22kHz tone. When the DSQIN pin is used for DiseqCTM encoding, 10 bits must be set to low. Complete two -way DiseqCTM 2.0 interface is completed by a built -in 22kHz tone detector. Its input pin (Detin) must be coupled to the Diseqctm bus, and the extracted PWK data can be performed on the DSQOUT pin (*).

In order to meet the two-way DiseqCTM 2.0 bus hardware requirements, an output R-L filter is required. LNBH21 with two output pins: VOTX used during tone transmission and VORX used when receiving tones. This allows 22kHz to pass through without any loss to R-L filter impedance (see page 5 Diseqc 2.0 application circuit). During the 22kHz transmission during the Diseqc 2.0 application in the 22kHz transmission during the DSQIN pin (or 10 I2C bits), the VOTX pin must be performed through the TTX I2C bit and 13/18V power supply and 22kHz tone. For zero shutdown, the 13/18V power supply is provided by V to LNBOTX must be provided to ORX through VOTX output. Once the audio transmission expires, V passes through the R-L filter. When LNBH21 is used for DISEQC 1.x applications, the R-L filter does not need (see Diseqc 1.x application circuit on page 5), the TTX I2C bit must always be kept at high level so that the VOTX output pins can provide 13/13/13// 18V power and 22kHz tone, which is opened by 2 DSQIN pins or 10 IC bits. All the functions of the IC are controlled by the I2CTM bus through the system register (SR, 8) to control the control bit). The same register can be read back, and the two digits will report the diagnosis status. When the IC is placed in the standby state (EN is low), the power block is disabled. When the regulator block is activated (EN is high), Can control the output logic to 13 or 18 v remote control through the VSEL bit (voltage selection). In addition, the LNBH21 is equipped with the LLC I2C bit, which can increase the selected voltage value (+1V). When VSEL 0,+1.5V When VSEL 1), compensate for excessive voltage reduction cable along the coaxial cable (LLC bits high level high (LLC bits high level high (LLC bits are high level high (LLC bits are high level high (LLC bits high level high (LLC bits are high level high (LLC bits high level high (LLC bits are high level high (LLC bits are high level high To.

Through the LLC bit, LNBH21 also meets the higher output voltage level of the US LNB power standard for 19.5V (typical values) (not 18V). Just set LLC 1 to VSEL 1. In order to improve the flexibility of design and allow new LNB remote control to implement standards, an analog modulation input pin (EXTM) can be used. The appropriate DC closed lock capacitor must be used to coupling the modulation signal source to the EXTM tube foot. In this case, the VOTX output must be set to ON by setting the TTX bit as high and in the process of tone transmission. When the external modulation is not used, the related pins can be kept open. The current restriction block is SOA type, which can be pins through dedicated ISEL pins. If ISEL keeps floating or connected voltage gt; 3.3V. When the ISEL pin is grounded. When the output port is short -circuited to the ground, the SOA current limitation block restrictions are short -circuit current (ISC) with voltage with a voltage of 13V or 18V, respectively to reduce the power dissipation. In addition, you can set a short -circuit current protection (simple current clamp) or dynamic through the PCL bit of the I2C SR; when the PCL (pulse current limit) bit is set to low, the overcurrent protection circuit is dynamic. Once the overload is detected, the output will be output. Close for a period of time, usually 900ms. At the same time, the OLF position of the system register is high. After this time, the output will be restored for a period of time T 1/10TOFF (typical values). At the end of TON, if the overload is still detected, the protective circuit will circulate again through TOFF and TON. No overload, restoring normal operation, and OLF are reset to low. The typical TON+TOFF time is 990ms, which is determined by the internal timer.

The current limit block is SOA type, which can be pins through dedicated ISEL pins. If ISEL keeps floating or connected voltage gt; 3.3V. When the ISEL pin is grounded. When the output port is short -circuited to the ground, the SOA current limitation block restrictions are short -circuit current (ISC) with voltage with a voltage of 13V or 18V, respectively to reduce the power dissipation. In addition, you can set a short -circuit current protection (simple current clamp) or dynamic through the PCL bit of the I2C SR; when the PCL (pulse current limit) bit is set to low, the overcurrent protection circuit is dynamic. Once the overload is detected, the output will be output. Close for a period of time, usually 900ms. At the same time, the OLF position of the system register is high. After this time, outputIt will be restored for a period of time t 1/10toff (typical value). At the end of TON, if the overload is still detected, the protective circuit will circulate again through TOFF and TON. No overload, restoring normal operation, and OLF are reset to low. The typical TON+TOFF time is 990ms, which is determined by the internal timer. This dynamic operation can greatly reduce power consumption in short circuit conditions, and at the same time ensure that excellent performance is started in most cases.

However, in some cases, the high -capacitance load at the output end may cause startup when selecting dynamic protection. This can solve the static mode (PCL high) by starting any power to start, and then switch to the dynamic mode (PCL low) after the selected quantity. In the static mode, when the current clamping limit is reached, the OLF bit becomes higher and the overload state is low. The IC can also prevent overheating: when the knot temperature exceeds 150 ° C (typical value), the boost converter and linear regulator are closed, and the OTF SR position is set to high. When normally, when the knot is cooled to 140 ° C (typical values), the operation is restored, and the OTF bit is reset to a low.

Note: External components need to meet the hardware requirements of the two -way DiseqCTM bus. Using this IC does not mean that the entire application fully meets the Diseqctm specification

I2C bus interface

data transmission from main μP to LNBH21 and Viceveersa interface The line SDA and SCL are composed (the upper pull resistor of the positive power supply voltage must be connected external). The validity of the data is shown in Figure 1 that the data on the SDA line must be stable during the clock's high cycle. The low state of the data cable will change only when the clock signal on the SCL line is low. Starting and stop conditions are shown in Figure 2. The starting condition is the conversion of the SDA line from high to low, while SCL is high. When the SCL is high, the stop condition is the conversion of the SDA line from low to high. Stop conditions must be sent before each startup condition. Each byte transmitted by byte format to SDA must contain 8 bits. There must be a answer to each byte. First transmit MSB.

It is admitted that during the confirmation of the clock pulse, the host (μP) sets the resistor high level on the SDA line (see Figure 3) one. The confirmed peripheral device (LNBH21) must be confirmed in the clock pulse in order to stabilize the SDA cable at a low level during the clock pulse period. The peripheral device must generate a response after receiving each byte, otherwise the SDA line will be kept at a high level in the ninth clock pulse time. In this case, the main transmitter can generate stop information to suspend transmission. LNBH21 does not generate confirm whether the VCC power supply is lower than the low -voltage lock threshold (6.7V typical value).

No response transmission

In order to avoid detecting the response of LNBH21, μP can be used more simpleTransmission: Just wait for a clock to confirm from the machine and send new data. Of course, this method is not easy to be protected by mistakes and reduces the antidity.

The interface protocol

The interface protocol includes: -Bear condition-chip address byte /11 (LSB bit decide to read ( 1)/write ( 0) transmission) -The data sequence (1 byte+confirmation) -Stop condition (p)

[ 123] R, W Reading and writing position; R Reading only

All bit reset at 0

Transmission data (i2C bus writing mode)

When the R/W bit in the chip address is set to 0, the system register (SR) LNBH21 that the main μP can write through the I2C bus. Only 6 of the 8 bits can be written by μP, because the remaining two are retained to the diagnostic sign and read only.

Receive data (I2C bus reading mode)

LNBH21 can provide a copy mode for the system register information to the host through the I2C bus. Reading mode is activated by sending a chip address set to 1 with R/W bit. After the main clock, LNBH21 emits a byte transmission on the SDA data bus (MSB)). In the ninth clock, the MCU host can: -Chat to confirm the reception, and start to send another byte from LNBH21 in this way; When the entire register is read back by μP, only OLF and OTF only read the diagnostic information about LNBH21. Unless there are other regulations, the value is a typical value.

Electric I2C interface reset

LNBH21 built -in I2C interface automatically reset when power is powered. As long as the VCC is lower than the underwriting threshold (6.7V typical values), the interface will not respond to any I2C command and system register (SR) to be initialized to a full zero, so as to keep the power block disabled. Once the VCC rises above 7.3V, the I2C interface starts to work, SR can be configured by the main power supply. This is due to the lag of 500 millivol to the UVL threshold to avoid power -on reset circuits.

PIN address

Connecting this pins to the GND chip I2C interface address is 0001000, but you can choose 4 different addresses to set the pin to 4 fixed voltage electrical electrical electrical electrical electrical electrical electrical electrical electrical electrical electrical electrical electricals Ping (see the table 10).

Diseqctm Implementation

LNBH21 By allowing

22kHz carrier simple PWK modulation/demodulation. PWK data uses logic levels compatible with 3.3 and 5V microcontrollers in LNBH21 and main μP. This data exchange is performed through two special pins DSQin and DSQOUT to maintain the timing relationship between PWK data and PWK modulation as accurate. These two pipes should be directly connected to the two I/O tube feet that are directly connected to μP, leaving the task to the resident firmware to encode and decode PWK data based on the DiseqC protocol. It is completely consistent, and only the use of LNBH21 does not mean that the system meets the specifications. System designers should also consider the hardware requirements of the bus; this can simply implement the terminal connection on the VO pin of the LNBH21 through the R-L. As shown in the typical application circuit on the page, 4 in order to avoid the R-L impedance during the audio transmission process. For any loss, LNBH21 has a dedicated output (VOTX). In the Diseqc 2.0 application, after connecting to the filter, the TTX SR bits must be set to high during the tone transmission (see Diseqc 2.O Operation on page 2 of the second page ofo operation, the explanation on page 2 of the 2o operation To. Unidirectional (1.x) Diesqc and non -Diseqc systems usually do not need this terminal, and VOTX pins can be directly connected to the LNB power port of the tunner (see Page 4 of the Diseqc 1.x application circuit above). There is no need for audio decoding, so the DETIN and DSQOUT tube feet can be provided by VOTX.

The electrical characteristics of the lnbp series (TJ 0 to 85 ° C, EN 1, TTX 0/1, dscin low, LLC ten pCl vSEL 0, vin 12V, IO 50mA, unless there are other regulations. See the software description of the I2C access system register).

Hot design description

During the normal operation period, the LNBH21 device consumes some power. Under the maximum rated output current (750 mAh), the voltage drop on the linear regulator causes total power consumption, usually 1.65W. The heat generated requires a suitable heat sink to maintain the knot temperature lower than the temperature protection threshold. Assuming that the internal temperature of the sheet of the set -top box is 45 ° C, the environmental temperature of the Radio Hong Kong must be less than 48 ° C/W. And this can easily achieve the use of a pore power package, which can be attached to a metal frame of a small radiator or a receiver. The power package on the surface paste must rely on the PCB thermal efficiency to usually have limited solutions. The easiest solution is to use a large, continuous GND layer copper area for the calorie of the heat dissipation IC body. If the RTHJ shell is equal to 2 ° C/W, the maximum temperature of the PCB heat sink is 46 ° C/W. This number is realized if you place at least 6.5cm2 in the bottom of the IC body, it can be achieved. This area can be the GND layer of the internal multi -layer PCB, or in the double -layer PCB, even in anotherThe position of a complete GND region IC on the side.In Figure 4, it shows the layout of a proposed PSO-20 package. The PCB layer connected to the GND and the square heat dissipation region are connected through 32 through-hole connections to fill it with welded.This layout, when L 25mm, can implement RTHC AMB about 32 ° C/W.Different layouts are also possible.However, the basic principles are recommended to maintain the integrated circuit and its basic exposure of the pads in the middle of the heat dissipation area; it provides as many pores as possible as possible as possible as possible without being interrupted by other copper.

Typical features (unless there are other regulations, TJ 25 ° C)