Features

● Completely conforming to IEEE 802.3U 10Base-T/100base-TX/FX

● Support automatic negotiation function, in line with IEEE 802.3u

● Complete integrated integration The physical layer single chip, the direct interface to the magnetism

● Integrate 10Base-T and 100Base-TX transceiver

● Optional relay or node mode

● FX mode The remote fault signal options

● Optional MII or RMII (reduced MII) interface, located at 100Base-TX

● 10Base-T to select GPSI (7 line) or MII mode.

● Optional twisted twisted line or fiber optic mode output

● You can select a full -duplex or half -duplex operation

● Mii management interface with shielding interrupt output [ 123]

● Provide a loop mode, which is convenient for system diagnosis

● LED status output indicator link/activity, Speed10/100 and full dual -workers/collision.

● 3.3V single power supply with a 0.35 μm CMOS process low power consumption

● Extremely low power consumption mode:

-The power reduction mode (cable detection)

- Power off mode

-1: 1 or 1.25: 1 The optional TX drive for transformer for additional power reduction.

● Compatible with 3.3V and 5.0V compatible I/O

● 48 -pin LQFP small packaging (1x1 cm)

General description

DM9161 is a physical layer, single-chip and low-power transceiver for 100Base-TX 100BASE-FX and 10Base-T operations. In terms of medium, it provides a direct interface for 100Base-TX fast Ethernet non-shielded twisted twisted twisted pair 5 cables (UTP5), or 10Base-T Ethernet UTP5/UTP3 cable. Through media independent interface (MII), DM9161 is connected to the media access control (MAC) layer to ensure the high interoperability of different suppliers.

DM9161 uses low -power, high -performance CMOS processes. It contains the 100BASE-TX function defined by the entire physical layer IEEEEEE802.3U, including the physical encoding subtrama (PCS), the physical medium connection (PMA), the bilateral physical medium related subtracement (TP-PMD), the 10Base-TX codec decoding decoding decoding decoding decoding decoding decoding decoding decoding ENC/DEC and twin -line media access units (TPMAU). DM9161 uses automatic media speedThe choice of agreement provides strong support for the automatic negotiation function. In addition, due to the built-in wave-shaped filter, DM9161 can transmit signals to medium without an external filter to transmit signals in 100Base-TX or 10Base-T Ethernet operation.

block figure

LED configuration

After power -on or software reset, by writing the PHY register, the LED flashes every 200ms. All LED tube feet are dual -function tube feet, which can be configured at high levels or low levels by lowering or high through corresponding places. If the pin is raised, the LED is in a low activation state after reset. Similarly, if the pin is pulled down, the high level of the light -emitting diode activates the high level.

Function description

DM9161 Express Ethernet single tablet transceiver provides the function specified in IEEE 802.3U, integrating a complete 100Base-TX module and and. A complete 10Base-T module. DM9161 provides the media independent interface (MII) defined in the IEEE 802.3U standard (Article 22).

DM9161 executes all PCS (physical encoding subtrays), PMA (physical media visits), TP-PMD (biper-twisted physical medium-related) subclase, 10BASE-T encoder/decoder, and twisted wire Media access unit (TPMAU) function. Figure 1 shows the main functional block implemented in DM9161.

MII interface

DM 9161 provides the media independent interface (MII) defined in the IEEE 802.3U standard. The purpose of the MII interface is to provide a simple and easy -to -implement connection between the MAC regulatory layer and PHY. MII aims to make the differences between various media transparent to the Mac subclase.

MII consists of semi -byte width receiving data bus, semi -byte width transmission data bus and control signal to facilitate data transmission between PHY and coordinated layers.

TXD (transmission data) is a semi -byte (4 digit) data that is synchronized with the adjustment subtrama relative to TXCLK. For each TXCLK cycle that asserts TXEN, PHY accepts TXD (3: 0) for transmission.

output TXCLK (transmitting clock) of the subtree layer is a continuous clock, providing regular reference for the transmission of TXEN, TXD, and TXER signals.

TXEN (transmission enabled) input from the Mac regulating subtree indicates that the MII is presented by semi -bytes in order to transmit on the physical media.

TXER (transmission coding error) conversionSynchronize with TXCLK. If the TXER is asserted for one or more clock cycles and the TXEN is asserted, the PHY will issue one or more symbols. These symbols are not part of the valid data separator set in a certain settings in the frame that is being transmitted.

RXD (receiving data) is a semi -byte (4 digit) data that regulates the sub -layer compared to RXCLK synchronous samples. For each RXCLK cycle that RXDV is asserted, RXD (3: 0) is transmitted from PHY to MAC regulatory subtraits from PHY.

RXCLK (receiving clock) output to Mac adjustment sub -layer is a consecutive clock, providing regular reference for the transmission of RXDV, RXD, and RXER signals.

RXDV (valid receiving data) entered from PHY indicates that PHY is being regulating and decoding a half byte to the MAC regulatory subtrama. In order to correctly interpret the receiving frame by coordinating the subtree, RXDV must include frames, no later than the beginning of the frame separation symbol, and excluding any end -of -end segmentation symbols.

Rxer (receiving error) conversion is synchronized with RXCLK. Rxer will be asserted to one or more clock cycles to detect errors somewhere in the frame of the adjusted subtrama to the frame from PHY to the adjustment subtra.

When the sending or receiving medium is not empty, the PHY asserts CRS (carrier detection). When the sending and receiving medium is free, the assertion is canceled. Figure 7-2 describes the behavior of CRS during 10Base-T and 100Base-TX transmission.

100Base-TX operation

100BASE-TX transmitter received 4-bit half byte data recorded at 25MHz clock records at MII, and at a speed of 100Mbps, 100Mbps speed 5-bit encoding MLT-3 signal output to the media. The clock circuit is converted to the 25MHz clock to 125MHz clock for internal use.

IEEE802.3U specification defines interfaces that have nothing to do with the media. The interface specifies the dedicated data bus and dedicated transmission data bus.

These two bus include various controls and signal indications for data transmission between DM9161 and the adjustment layer.

100Base-TX transmission

100Base-TX transmitter consists of a function block shown in Figure 7-3. The 100Base-TX sending section converts the 4-bit synchronous data provided by the MII to the serial data stream of the mLT-3125, one million symbols per second.

The box diagram in Figure 7-3 provides an overview of the function block contained in the transmission part. Part of the transmitter contains the following functionsBlock:

-4B5B encoder

-The disturburator

-Tong converter

-NRZ to NRZI encoder

] -NRZI to MLT-3

-MLT-3 driver

4B5B encoder

4B5B encoder 4-bit (4B) half-character generated by the MAC adjustment layer The data converted into 5-digit (5B) code group for transmission. See Table 7-1. This conversion is necessary to combine control and group data in the code group. The 4B5B encoder uses the J/K code group to replace the top 8 digits of the MAC front guide code with the J/K code group (11000 10001). The 4B5B encoder continues to replace the subsequent 4B front code and data semi -bytes with the corresponding 5B code group. At the end of the sending packet, when the sending of the enable signal from the MAC regulatory layer is sent, the 4B5B encoder injected the T/R code group to represent the end of the frame (0110100111). After the T/R code group is paired, the 4B5B encoder continues to inject free data into the sending data stream until it is seized and the next sending group is detected.

DM9161 includes a bypass 4B5B conversion option in the 100Base-TX transmitter to support applications that do not require 4B5B conversion in 100Mbps relay.

Drivers

In the 100Base-TX operation, the disturber needs to control the radiation emission (EMI) by the spectrum distribution energy on the media connector and the twisted cable.

The total energy presented to the cable through the disorder of the data is randomly distributed within a wider frequency range. If there is no spoiler, under the frequency related to repeated 5B sequences (such as continuous transmission of idle symbols), the peak of energy on the cable may exceed the limitation of FCC. The output of the disturbor is combined with the NRZ5B data from the code group encoder through the heterogeneous or logical function. As a result, an additional data stream has enough randomness to reduce radiation launch at critical frequency.

Concurrent converter

Parallel to the serial converter from the coder to receive parallel 5B plus the data and serialize it (convert it from parallel data to serial data streaming To. Then present the serialized data stream to NRZ to NRZI encoder block

NRZ to NRZI encoder

Since the transmission data stream has been disrupted and serialized, the data must be conducted on the data NRZI Coding is compatible with TP-PMD standards for 100BASE-TX transmission through 5 types of non-shielding bipyle-twisted cables.

MLT-3 converter

MLT-3 conversion is by converting data output from the NRZI encoder into two alternate.The binary data stream of the position logic 1 event is achieved.

MLT-3 drive

The two binary data streams created at the MLT-3 converter were sent to the twisted line output drive. Alternately drive any side of the primary winding of the transformer to generate the MLT-3 signal of the minimum current. The box diagram of the MLT-3 converter is shown in Figure 7-4.

4B5B code group

100Base-TX receiver

100Base TX receiver contains more than In this functional block, these functional blocks convert the additional 125MB/s serial data to synchronize 4 -digit semi -byte data, and then provide it to MII.

The receiving part contains the following functional blocks:

-The adaptive balancer

-MLT-3 to NRZI decoder

-The clock recovery module [123 ]

-NRZI to NRZ decoder

-Candarin

-Liexer

-code group alignment

-4B5B decoder [ 123]

Signal detection

The signal detection function conforms to ANSI XT12 TP-PMD 100Base-TX standard voltage threshold and timing parameters.

Adaptive balancer

When the data is transmitted at high speed through the copper twisted cable, the frequency -based attenuation becomes a problem. In the high -speed twisted signaling, due to the randomness of adding data flow, the frequency content of transmission signals during normal operation will change greatly. This change must be compensated to the attenuation of the signal attenuation caused by frequency changes to ensure the integrity of the receiving data. In order to ensure the transmission quality of MLT-3 coding, compensation must be able to adapt to different cable lengths and cable types according to the installation environment. To choose a long cable length for the given embodiment, a large amount of compensation is required. This will be excessive lethal. On the contrary, choosing a short or intermediate cable length that requires less compensation will lead to insufficient compensation of longer cables. Therefore, compensation or equilibrium must be adaptive to ensure that the appropriate adjustment of the receiving signal has nothing to do with the length of the cable.

MLT-3 to NRZI decoder

DM9161 MLT-3 information decoding from digital adaptive balancer in the future is NRZI data. The relationship between NRZI and MLT-3 data is shown in Figure 7-4.

Clock recovery module

The clock recovery module receives NRZI data from MLT-3 to NRZI decoder. Clock recovery moduleLock the data stream and extract the 125MHz reference clock. Extracted and synchronized clocks and data were provided to NRZI-to-NRZ decoder.

NRZI to NRZ

The transmission data stream requires NRZI encoding to compatible with the TP-PMD standards transmitted by 100Base-TX transmission through 5 types of non-shielded twisting cables. This conversion process must be reversed on the receiving end. NRZI to NRZ decoder receives the NRZI data stream from the clock recovery module and converts it to the NRZ data stream to present the serial -to -parallel conversion block.

String and connect

String and converter receives serial data streams from the NRZI-NRZ converter, and converts the data to parallel data to present to the interpreter.

Amblieter

Since the radiation launch of the launch data flow is required, the receiver must be interpreted on the receiving data stream. The disturbing device receives a parallel parallel data stream from the string and converter, the data stream is relieved, and the data stream is present to the code set.

Code group alignment

Code group alignment block from 5B data from the unresolved alignment and converting it into a 5B code set data. The code group alignment occurs after the J/K is detected, and the subsequent data will be aligned on the fixed boundary.

4B5B decoder

The function of the 4B5B decoder is as a search table, which converts the transmitted 5B code group to 4B (semi -byte) data. When receiving the frame, the first two 5 -bit code group received is the starting frame separation symbol (J/K symbol). The J/K symbols were peeled off and two and a half bytes of the preliminary mode were replaced. The last two code sets are frame ending symbols (T/R symbols).

T/R symbol pairs are also peeled from semi -bytes presented to the adjustment layer.

10Base-T operation

10Base-T transcetator meets the IEEE 802.3U standard. When DM9161 works in 10Base-T mode, the encoding scheme is Manchester. The data processed for transmission is provided to the MII interface in a semi -byte format, converted into serial bittios, and then encoded Manchester. At the time of receiving, the Bit flow coded by Manchester was decoded and converted into a semi -by -line format to present it to the MII interface.

Crash detection

For semi -double operations, conflicts will be detected when the semi -dual -work operation is activated at the same time. When the collision is detected, the COL signal on the MII interface will report it. Disable collision detection in full -duplex operations.

Carrier sensing

During the transmission or receiving data, the carrier detection (CRS) was interrupted in the half -worker operation. In the full dual -working mode, only the CRS is asserted during the receiving operation.

Automatic negotiation

The goal of automatic negotiation is to provide a method to exchange information between sections, and automatically configure two devices to maximize their ability to use them. It should be noted that automatic negotiation does not have the characteristics of the test chain section. The automatic negotiation function provides a method for the device for the operation mode supported by the remote link partner, confirming and understanding the general operation mode, and refusing to sharing the operation mode. This allows the equipment at both ends of the segment to establish a link with the best public operation mode. If there are more than one public model between the two devices, a mechanism is provided to allow the device to use the predetermined priority analysis function analysis as a single operation mode.

Automatic negotiation

Automatic negotiation also provides parallel detection functions for equipment that does not support automatic negotiation functions. During parallel testing, the configuration information is not exchanged, but instead checks the receiving signal. If the signal is found to match the technology supported by the receiving device, the technology will be automatically established using the technology. A device that does not support automatic negotiation models, but does not support this model.

MII serial management

MII serial management interface consists of a serial management interface of the data interface, basic register set and the storage set. Through this interface, you can control and configure multiple PHY devices, obtain status and error information, and determine the types and functions of the PHY device connected.

DM9161 management function corresponds to the MII specifications of IEEE 802.3U-1995 (Article 22), suitable for register 0 to 6 and supplier special registers 16, 17, 18, 21, 22, 23, and 24.

In reading/writing operations, the length of the management data frame is 64 -bit, starting from 32 continuous logic 1 digits (front guide code) on the MDC synchronization clock cycle. The beginning of the frame separation symbol (SFD) is represented by a u0026 lt; 01 u0026 gt; the follow -up operating code (OP): u0026 lt; 10 u0026 gt; indicating the reading operation, u0026 lt; 01 u0026 gt; For reading operations, provide 2 -bit turn (TA) files between the register address and data fields for MDIO to avoid fighting. After the turnover time, read or write 16 -bit data from the management register.

Serial management interface

The serial control interface uses a simple two -line serial interface to obtain and control the state of the physical layer through the MII interface. The serial control interface consists of MDC (managing data clock) and MDI/O (managing data input/output) signals.

The MDIO pin is two -way, which can be shared by 32 devices.

Management interface-Reading frame structure

Management interface-writing frame structure

Power reduction mode

Signal detection circuit is alwaysOpen it to monitor whether there is signal in the media. When the cable is disconnected, the DM9161 will automatically turn off the power and enter the power reduction mode. Whether it is running an automatic negotiation or a mandatory mode. In the power reduction mode, the transmitting circuit will continue to send a fast link pulse with the minimum power consumption. If a valid signal is detected from the medium, it may be the N-way fast link pulse, the 10Base-T normal link pulse or the 100Base-TX MLT3 signal, the device will wake up and restore the normal working mode.

Automatic power reduction mode can be disabled by writing 0 to the register 16.4.

Power failure mode

By setting the reg.0.11 to 1 or pulling the PWRDWN pin to enter the power -off mode, this will disable all sending except the MDC/MDIO management interface And receiving function and MII interface function.

Reduce the transmitting power mode

By designing 1.25: 1 turning magnetic resistance on the TX side, the 8.5kΩ resistor is used on the BGRES and BGRESG pin, and the TX+/TX raises the resistor from the resistance from the resistance from the resistance from the resistance from The 50Ω is changed to 78Ω, which can get additional launch power. This configuration can reduce the launch power by about 20%.

Application notice

Network interface signal routing

The transformer is as close to the RJ-45 connector as much as possible. All 50Ω resistors are close to DM9161 RX ± and TX ± pins as possible. The lines from RX ± and TX ± transformers should be tightly connected to the transformer directly to the ground. The designer should pay attention not to cross and receive the pair. As always, try to avoid over -holes. Except for the TX ± and RX ± pairs between the RJ-45 to the transformer and the transformer to the DM9161, there should be no signal of the network interface. There should be no ground floor in the area below the side of the network, including the area under the RJ-45 connector (refer to Figure 10-1 and 10-2). Keep the chassis ground away from all activation signals. The RJ-45 connector and any unused pin shall be connected to the chassis through the resistor network and the 2KV bypass electrical container.

The gap resistor should be as close to the pin 47 and 48 as possible (reference Figure 10-1 and 10-2). Designers should not run any high -speed signals near the gap resistance.

10base-t/100base-tx application

10base-t/100base-tx (power reduction application)

100base-fx application

Power decoupling capacitor

davicom semiconductorThe best distance from all positions is less than 3 mm). The decoupling capacitors of all power pins are placed by 0.1 μF or 0.01 μF according to the suggestion, and the power board is close to the DM9161 as much as possible (according to the design layout requirements).

Plane layout

For cards that do not meet specific FCC regulations (part 15), it is recommended to use a single -connected ground plane method. Minimize electromagnetic interference. Poor ground plane division may lead to more EMI launch in Figures 10-6 and Figure 10-7, which may make the network interface scheme.

Power plane division

Power plane should be roughly stated in Figure 10-8 and 10-9. The impedance of the iron oxygen magnetic beads should be at least 75Ω at 100MHz. A suitable bead is Panasonic's surface hill bead, part number.

Excl4532U or the same product. 10 μF, 0.1 μF, and 0.01 μF electrolytic barrier container should be connected between the DVDD and DGND on each side of the iron oxygen magnetic bead.

Magnetic selection guide

See Table 10-2. The transformers that meet these requirements have a variety of magnetic manufacturers. Before the application is used, the designer should test and identify all magnetic materials. The transformers listed in Table 10-2 are electrical equivalent, but may not be targeted at foot equivalent.

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